The Suitability of the SPR-MP Method to Evaluate the Reliability of Logic Circuits. - Matheus F. Pontes; Paulo F. Butzen; Rafael B. Schvittz; Leomar S. da Rosa Jr.; Denis Teixeira Franco (ICECS, 2018)

Reliability evaluation of circuits designed in multi- and single-stage versions. - Rafael B. Schvittz; Matheus F. Pontes; Cristina Meinhardt; Denis Teixeira Franco; Lirida A. B. Naviner; Leomar S. da Rosa; Paulo F. Butzen (LASCAS, 2018)

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. - Shubham Rai; Walter Lau Neto; Yukio Miyasaka; Xinpei Zhang; Mingfei Yu; Qingyang Yi; Masahiro Fujita; Guilherme B. Manske; Matheus F. Pontes; Leomar S. da Rosa; Marilton S. de Aguiar; Paulo F. Butzen; et al. (DATE, 2021)

Fault Tolerance Evaluation of Different Majority Voter Designs. - Ingrid F. V. Oliveira; Matheus F. Pontes; Rafael B. Schvittz; Leomar S. da Rosa Jr.; Paulo F. Butzen; Rafael Iankowski Soares (ISCAS, 2022)

The Impact of Logic Gates Susceptibility in Overall Circuit Reliability Analysis. - Matheus F. Pontes; Ingrid F. V. Oliveira; Rafael B. Schvittz; Leomar Soares da Rosa Jr.; Paulo F. Butzen (ISCAS, 2022)

Single-Pass Critical Input Vectors Detection. - João Machado; Matheus F. Pontes; Paulo Flores; Paulo F. Butzen; Leomar Rosa (LASCAS, 2025)