BaBaNoC: An asynchronous network-on-chip described in Balsa. - Matheus T. Moreira; Felipe G. Magalhaes; Matheus Gibiluka; Fabiano Hessel; Ney Laert Vilar Calazans (RSP, 2013)

Blade - A Timing Violation Resilient Asynchronous Template. - Dylan Hand; Matheus Trevisan Moreira; Hsin-Ho Huang; Danlei Chen; Frederico Butzke; Zhichao Li; Matheus Gibiluka; Melvin A. Breuer; Ney Laert Vilar Calazans; Peter A. Beerel (ASYNC, 2015)

A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework. - Matheus Gibiluka; Matheus Trevisan Moreira; Ney Laert Vilar Calazans (DSD, 2015)

BAT-Hermes: A transition-signaling bundled-data NoC router. - Matheus Gibiluka; Matheus Trevisan Moreira; Fernando Gehm Moraes; Ney Laert Vilar Calazans (LASCAS, 2015)

Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications. - Ramy N. Tadros; Weizhe Hua; Matheus Gibiluka; Matheus T. Moreira; Ney Laert Vilar Calazans; Peter A. Beerel (ASYNC, 2016)

Design and analysis of the HF-RISC processor targeting voltage scaling applications. - Felipe Todeschini Bortolon; Sergio Johann Filho; Matheus Gibiluka; Sergio Bampi; Ney Laert Vilar Calazans; Fabiano Passuelo Hessel; Matheus Trevisan Moreira (SBCCI, 2016)

A standard cell characterization flow for non-standard voltage supplies. - Matheus Gibiluka; Matheus Trevisan Moreira; Walter Lau Neto; Ney Laert Vilar Calazans (SBCCI, 2016)