Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques. - Julian J. H. Pontes; Matheus T. Moreira; Rafael Soares; Ney Laert Vilar Calazans (ISVLSI, 2008)

Hermes-A - An Asynchronous NoC Router with Distributed Routing. - Julian J. H. Pontes; Matheus T. Moreira; Fernando Moraes 001; Ney Calazans (PATMOS, 2010)

Hermes-AA: A 65nm asynchronous NoC router with adaptive routing. - Julian J. H. Pontes; Matheus T. Moreira; Fernando Moraes 001; Ney Calazans (SoCC, 2010)

Adapting a C-element design flow for low power. - Matheus T. Moreira; Bruno Cruz de Oliveira; Julian J. H. Pontes; Fernando Moraes 001; Ney Calazans (ICECS, 2011)

A 65nm standard cell set and flow dedicated to automated asynchronous circuits design. - Matheus T. Moreira; Bruno Cruz de Oliveira; Julian J. H. Pontes; Ney Calazans (SoCC, 2011)

A generic FPGA emulation framework. - Fernando Gehm Moraes; Matheus T. Moreira; Carlos Lucas; D. Correa; Douglas de O. Cardoso; Maurício Cecílio Magnaguagno; Guilherme M. Castilhos; Ney Laert Vilar Calazans (ICECS, 2012)

Electrical characterization of a C-Element with LiChEn. - Matheus T. Moreira; Ney Laert Vilar Calazans (ICECS, 2012)

Return-to-One DIMS logic on 4-phase m-of-n asynchronous circuits. - Matheus T. Moreira; Ricardo A. Guazzelli; Ney Laert Vilar Calazans (ICECS, 2012)

Impact of C-elements in asynchronous circuits. - Matheus T. Moreira; Bruno Cruz de Oliveira; Fernando Moraes 001; Ney Calazans (ISQED, 2012)

Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes. - Matheus T. Moreira; Ricardo A. Guazzelli; Ney Laert Vilar Calazans (SBCCI, 2012)

Charge sharing aware NCL gates design. - Matheus T. Moreira; Bruno S. Oliveira; Fernando Gehm Moraes; Ney Laert Vilar Calazans (DFTS, 2013)

LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries. - Matheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ney Laert Vilar Calazans; Luciano Copello Ost (DSD, 2013)

Voltage scaling on C-elements: A speed, power and energy efficiency analysis. - Matheus Trevisan Moreira; Ney Laert Vilar Calazans (ICCD, 2013)

Evaluating the scalability of test buses. - Alexandre M. Amory; Matheus T. Moreira; Ney Laert Vilar Calazans; Fernando Gehm Moraes; Cristiano Lazzari; Marcelo Soares Lubaszewski (ISSoC, 2013)

Design of standard-cell libraries for asynchronous circuits with the ASCEnD flow. - Matheus Trevisan Moreira; Ney Laert Vilar Calazans (ISVLSI, 2013)

Design of NCL gates with the ASCEnD flow. - Matheus T. Moreira; Carlos Henrique Menezes Oliveira; Ricardo C. Porto; Ney Laert Vilar Calazans (LASCAS, 2013)

NCL+: Return-to-one Null Convention Logic. - Matheus T. Moreira; Carlos Henrique Menezes Oliveira; Ricardo C. Porto; Ney Laert Vilar Calazans (MWSCAS, 2013)

BaBaNoC: An asynchronous network-on-chip described in Balsa. - Matheus T. Moreira; Felipe G. Magalhaes; Matheus Gibiluka; Fabiano Hessel; Ney Laert Vilar Calazans (RSP, 2013)

Lasio 3D NoC vertical links serialization: Evaluation of latency and buffer occupancy. - Yan Ghidini; Matheus T. Moreira; Lucas Brahm; Thais Webber; Ney Calazans; César A. M. Marcon (SBCCI, 2013)

A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design. - Matheus Trevisan Moreira; Michel Evandro Arendt; Ricardo Aquino Guazzelli; Ney Laert Vilar Calazans (ASYNC, 2014)

Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible? - Matheus T. Moreira; Augusto Neutzling; Mayler G. A. Martins; André Inácio Reis; Renato P. Ribas; Ney Calazans (ASYNC, 2014)

Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesis. - Matheus Trevisan Moreira; Ricardo Aquino Guazzelli; Guilherme Heck; Ney Laert Vilar Calazans (ACM Great Lakes Symposium on VLSI, 2014)

A design flow for physical synthesis of digital cells with ASTRAN. - Adriel Ziesemer; Ricardo Reis 001; Matheus T. Moreira; Michel Evandro Arendt; Ney Laert Vilar Calazans (ACM Great Lakes Symposium on VLSI, 2014)

Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design. - Matheus T. Moreira; Julian J. H. Pontes; Ney Laert Vilar Calazans (ISQED, 2014)

Automatic layout synthesis with ASTRAN applied to asynchronous cells. - Adriel Ziesemer; Ricardo Reis 001; Matheus T. Moreira; Michel Evandro Arendt; Ney Laert Vilar Calazans (LASCAS, 2014)

Schmitt trigger on output inverters of NCL gates for soft error hardening: Is it enough? - Ricardo A. Guazzelli; Guilherme Heck; Matheus T. Moreira; Ney Laert Vilar Calazans (LATW, 2014)

Automated Synthesis of Cell Libraries for Asynchronous Circuits. - Matheus Trevisan; Michel Evandro Arendt; Adriel Ziesemer; Ricardo Augusto da Luz Reis; Ney Laert Vilar Calazans (SBCCI, 2014)

Advances on the state of the art in QDI design. - Matheus T. Moreira; Ney Laert Vilar Calazans (VLSI-SoC, 2014)

Spatially Distributed Dual-Spacer Null Convention Logic Design. - Matheus Trevisan Moreira; Guilherme Trojan; Fernando Gehm Moraes; Ney Laert Vilar Calazans (J. Low Power Electron., 2014)

Beware the Dynamic C-Element. - Matheus Trevisan Moreira; Fernando Gehm Moraes; Ney Laert Vilar Calazans (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Performance Optimization and Analysis of Blade Designs under Delay Variability. - Dylan Hand; Hsin-Ho Huang; Benmao Cheng; Yang Zhang 014; Matheus Trevisan Moreira; Melvin A. Breuer; Ney Laert Vilar Calazans; Peter A. Beerel (ASYNC, 2015)

Blade - A Timing Violation Resilient Asynchronous Template. - Dylan Hand; Matheus Trevisan Moreira; Hsin-Ho Huang; Danlei Chen; Frederico Butzke; Zhichao Li; Matheus Gibiluka; Melvin A. Breuer; Ney Laert Vilar Calazans; Peter A. Beerel (ASYNC, 2015)

Design and Analysis of Testable Mutual Exclusion Elements. - Yang Zhang 014; Leandro S. Heck; Matheus T. Moreira; David Zar; Melvin A. Breuer; Ney Laert Vilar Calazans; Peter A. Beerel (ASYNC, 2015)

A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework. - Matheus Gibiluka; Matheus Trevisan Moreira; Ney Laert Vilar Calazans (DSD, 2015)

TDTB error detecting latches: Timing violation sensitivity analysis and optimization. - Matheus T. Moreira; Dylan Hand; Peter A. Beerel; Ney Laert Vilar Calazans (ISQED, 2015)

A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies. - Ajay Singhvi; Matheus T. Moreira; Ramy N. Tadros; Ney Laert Vilar Calazans; Peter A. Beerel (ISVLSI, 2015)

BAT-Hermes: A transition-signaling bundled-data NoC router. - Matheus Gibiluka; Matheus Trevisan Moreira; Fernando Gehm Moraes; Ney Laert Vilar Calazans (LASCAS, 2015)

A digitally controlled oscillator for fine-grained local clock generators in MPSoCs. - Guilherme Heck; Leandro S. Heck; Matheus T. Moreira; Fernando Gehm Moraes; Ney Laert Vilar Calazans (LASCAS, 2015)

SDDS-NCL Design: Analysis of Supply Voltage Scaling. - Ricardo A. Guazzelli; Fernando Gehm Moraes; Ney Laert Vilar Calazans; Matheus T. Moreira (SBCCI, 2015)

Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits. - Guilherme Heck; Leandro S. Heck; Ajay Singhvi; Matheus T. Moreira; Peter A. Beerel; Ney Laert Vilar Calazans (VLSID, 2015)

Static Differential NCL Gates: Toward Low Power. - Matheus Trevisan Moreira; Michel Evandro Arendt; Fernando Gehm Moraes; Ney Laert Vilar Calazans (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications. - Ramy N. Tadros; Weizhe Hua; Matheus Gibiluka; Matheus T. Moreira; Ney Laert Vilar Calazans; Peter A. Beerel (ASYNC, 2016)

ASCEnD-FreePDK45: An open source standard cell library for asynchronous design. - Carlos Henrique Menezes Oliveira; Matheus T. Moreira; Ricardo A. Guazzelli; Ney Laert Vilar Calazans (ICECS, 2016)

The HF-RISC processor: Performance assessment. - Sergio Johann Filho; Matheus T. Moreira; Ney Laert Vilar Calazans; Fabiano Passuelo Hessel (LASCAS, 2016)

Optimizing cell area by applying an alternative transistor folding technique in an open source physical synthesis CAD tool. - Gustavo H. Smaniotto; Joao Junior da Silva Machado; Matheus T. Moreira; Adriel Mota Ziesemer; Felipe S. Marques 001; Leomar S. da Rosa Jr. (LASCAS, 2016)

Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding. - Gustavo H. Smaniotto; Matheus T. Moreira; Adriel Mota Ziesemer; Felipe S. Marques 001; Leomar S. da Rosa (MWSCAS, 2016)

Design and analysis of the HF-RISC processor targeting voltage scaling applications. - Felipe Todeschini Bortolon; Sergio Johann Filho; Matheus Gibiluka; Sergio Bampi; Ney Laert Vilar Calazans; Fabiano Passuelo Hessel; Matheus Trevisan Moreira (SBCCI, 2016)

A standard cell characterization flow for non-standard voltage supplies. - Matheus Gibiluka; Matheus Trevisan Moreira; Walter Lau Neto; Ney Laert Vilar Calazans (SBCCI, 2016)

A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits. - Ajay Singhvi; Matheus T. Moreira; Ramy N. Tadros; Ney Laert Vilar Calazans; Peter A. Beerel (ACM J. Emerg. Technol. Comput. Syst., 2016)

A processor for IoT applications: An assessment of design space and trade-offs. - Sergio Johann Filho; Matheus T. Moreira; Leandro S. Heck; Ney Laert Vilar Calazans; Fabiano Passuelo Hessel (Microprocess. Microsystems, 2016)

A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI. - Ramy N. Tadros; Weizhe Hua; Matheus T. Moreira; Ney Laert Vilar Calazans; Peter A. Beerel (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Testable MUTEX Design. - Yang Zhang 014; Leandro S. Heck; Matheus T. Moreira; David Zar; Melvin A. Breuer; Ney Laert Vilar Calazans; Peter A. Beerel (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Asynchronous circuits: innovations in components, cell libraries and design templates. - Matheus Trevisan Moreira (2016)

Hardening C-elements against metastability. - Leandro S. Heck; Matheus T. Moreira; Ney Laert Vilar Calazans (ICECS, 2017)

A post-processing methodology to improve the automatic design of CMOS gates at layout-level. - Gustavo H. Smaniotto; Regis Zanandrea; Maicon Schneider Cardoso; Renato Souza de Souza; Matheus T. Moreira; Felipe S. Marques 001; Leomar S. da Rosa Jr. (ICECS, 2017)

Post-processing of supergate networks aiming cell layout optimization. - Gustavo H. Smaniotto; Regis Zanandrea; Maicon Schneider Cardoso; Renato Souza de Souza; Matheus T. Moreira; Felipe S. Marques 001; Leomar S. da Rosa Jr. (ISCAS, 2017)

A comparison of asynchronous QDI templates using static logic. - Ricardo A. Guazzelli; Matheus T. Moreira; Ney Laert Vilar Calazans (LASCAS, 2017)

Transistor placement strategies for non-series-parallel cells. - Maicon Schneider Cardoso; Gustavo H. Smaniotto; Joao Junior da Silva Machado; Matheus T. Moreira; Leomar S. da Rosa; Felipe de Souza Marques (MWSCAS, 2017)

Estimation methods for static noise margins in CMOS subthreshold logic circuits. - Felipe T. Bortolon; Fernando Gehm Moraes; Matheus T. Moreira; Sergio Bampi (SBCCI, 2017)

Sleep convention logic isochronic fork: an analysis. - Ricardo A. Guazzelli; Matheus T. Moreira; Walter Lau Neto; Ney Laert Vilar Calazans (SBCCI, 2017)

Optimized Design of an LSSD Scan Cell. - Leonardo Rezende Juracy; Matheus Trevisan Moreira; Felipe Augusto Kuentzer; Alexandre de Morais Amory (IEEE Trans. Very Large Scale Integr. Syst., 2017)

An LSSD Compliant Scan Cell for Flip-Flops. - Leonardo Rezende Juracy; Matheus T. Moreira; Felipe A. Kuentzer; Fernando Gehm Moraes; Alexandre M. Amory (ISCAS, 2018)

Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient Template. - Felipe A. Kuentzer; Leonardo Rezende Juracy; Matheus T. Moreira; Alexandre M. Amory (SBCCI, 2018)

Libra: An Automatic Design Methodology for CMOS Complex Gates. - Maicon Schneider Cardoso; Gustavo H. Smaniotto; Andrei A. O. Bubolz; Matheus T. Moreira; Leomar S. da Rosa Jr.; Felipe de Souza Marques (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization. - Matheus T. Moreira; Peter A. Beerel; Marcos L. L. Sartori; Ney Laert Vilar Calazans (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A DfT Insertion Methodology to Scannable Q-Flop Elements. - Leonardo Rezende Juracy; Matheus T. Moreira; Felipe A. Kuentzer; Alexandre M. Amory (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools. - Marcos L. L. Sartori; Rodrigo N. Wuerdig; Matheus T. Moreira; Ney Laert Vilar Calazans (ASYNC, 2019)

Test Oriented Design and Layout Generation of an Asynchronous Controller for the Blade Template. - Felipe A. Kuentzer; Leonardo Rezende Juracy; Matheus T. Moreira; Alexandre M. Amory (ASYNC, 2020)

Chronos Link: A QDI Interconnect for Modern SoCs. - Matheus Trevisan Moreira; Stefano Giaconi (ASYNC, 2020)

A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow. - Marcos L. L. Sartori; Matheus T. Moreira; Ney Laert Vilar Calazans (ASYNC, 2020)

Leveraging QDI Robustness to Simplify the Design of IoT Circuits. - Marcos L. L. Sartori; Rodrigo N. Wuerdig; Matheus T. Moreira; Sergio Bampi; Ney Laert Vilar Calazans (ISCAS, 2020)

A Survey of Aging Monitors and Reconfiguration Techniques. - Leonardo Rezende Juracy; Matheus Trevisan Moreira; Alexandre de Morais Amory; Fernando Gehm Moraes (CoRR, 2020)

Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization. - Walter Lau Neto; Matheus Trevisan Moreira; Luca G. Amarù; Cunxi Yu; Pierre-Emmanuel Gaillardon (ASP-DAC, 2021)

SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping. - Walter Lau Neto; Matheus T. Moreira; Yingjie Li; Luca G. Amarù; Cunxi Yu; Pierre-Emmanuel Gaillardon (DAC, 2021)

Quasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison. - Taciano A. Rodolfo; Marcos L. L. Sartori; Matheus T. Moreira; Ney Laert Vilar Calazans (ISCAS, 2021)

A TensorFlow and System Simulator Integration Approach to Estimate Hardware Metrics of Convolution Accelerators. - Leonardo Rezende Juracy; Matheus T. Moreira; Alexandre M. Amory; Fernando Gehm Moraes (LASCAS, 2021)

A High-Level Modeling Framework for Estimating Hardware Metrics of CNN Accelerators. - Leonardo Rezende Juracy; Matheus Trevisan Moreira; Alexandre de Morais Amory; Alexandre F. Hampel; Fernando Gehm Moraes (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries. - Matheus Trevisan Moreira; William Koven; Tony F. Wu; Huseyin Ekin Sumbul; Edith Beigné (ASYNC, 2023)

Validating an Automated Asynchronous Synthesis Environment with a Challenging Design: RISC-V. - Willian Analdo Nunes; Marcos Luiggi Lemos Sartori; Matheus Trevisan Moreira; Fernando Gehm Moraes; Ney Laert Vilar Calazans (SBCCI, 2023)

11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint. - Tony F. Wu; Huichu Liu; Huseyin Ekin Sumbul; Lita Yang; Dipti Baheti; Jeremy Coriell; William Koven; Anu Krishnan; Mohit Mittal; Matheus Trevisan Moreira; Max Waugaman; Laurent Ye; et al. (ISSCC, 2024)

A 3D Design Methodology for Integrated Wearable SoCs: Enabling Energy Efficiency and Enhanced Performance at Iso-Area Footprint. - Huseyin Ekin Sumbul; Arne Symons; Lita Yang; Huichu Liu; Tony F. Wu; Matheus Trevisan Moreira; Debabrata Mohapatra; Abhinav Agarwal; Kaushik Ravindran; Chris Thompson; Yuecheng Li; Edith Beigné (DATE, 2025)