Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh. - Matt Grange; Awet Yemane Weldezion; Dinesh Pamunuwa; Roshan Weerasekera; Zhonghai Lu; Axel Jantsch; Dave Shippen (3DIC, 2009)

Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits. - Roshan Weerasekera; Matt Grange; Dinesh Pamunuwa; Hannu Tenhunen; Li-Rong Zheng 001 (3DIC, 2009)

Scalability of network-on-chip communication architecture for 3-D meshes. - Awet Yemane Weldezion; Matt Grange; Dinesh Pamunuwa; Zhonghai Lu; Axel Jantsch; Roshan Weerasekera; Hannu Tenhunen (NOCS, 2009)

On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits. - Roshan Weerasekera; Matt Grange; Dinesh Pamunuwa; Hannu Tenhunen (DATE, 2010)

Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning. - Matthew Grange; Axel Jantsch; Roshan Weerasekera; Dinesh Pamunuwa (ICCAD, 2011)

Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks. - Matt Grange; Roshan Weerasekera; Dinesh Pamunuwa; Axel Jantsch; Awet Yemane Weldezion (NOCS, 2011)

3-D integration and the limits of silicon computation. - Dinesh Pamunuwa; Matthew Grange; Roshan Weerasekera; Axel Jantsch (VLSI-SoC, 2011)

The Promises and Limitations of 3-D Integration. - Axel Jantsch; Matthew Grange; Dinesh Pamunuwa (3D Integration for NoC-based SoC Architectures, 2011)

A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns. - Awet Yemane Weldezion; Matt Grange; Dinesh Pamunuwa; Axel Jantsch; Hannu Tenhunen (3DIC, 2013)

Zero-load predictive model for performance analysis in deflection routing NoCs. - Awet Yemane Weldezion; Matt Grange; Axel Jantsch; Hannu Tenhunen; Dinesh Pamunuwa (Microprocess. Microsystems, 2015)