Design Optimization for High-speed Per-address Two-level Branch Predictors. - I-Cheng K. Chen; Chih-Chieh Lee; Matt Postiff; Trevor N. Mudge (ICCD, 1997)

Performance Limits of Trace Caches. - Matt Postiff; Gary S. Tyson; Trevor N. Mudge (J. Instr. Level Parallelism, 1999)

The limits of instruction level parallelism in SPEC95 applications. - Matthew A. Postiff; David A. Greene; Gary S. Tyson; Trevor N. Mudge (SIGARCH Comput. Archit. News, 1999)

The store-load address table and speculative register promotion. - Matt Postiff; David A. Greene; Trevor N. Mudge (MICRO, 2000)

Integrating superscalar processor components to implement register caching. - Matt Postiff; David A. Greene; Steven E. Raasch; Trevor N. Mudge (ICS, 2001)

Compiler and microarchitecture mechanisms for exploiting registers to improve memory performance. - Matt Postiff (2001)