Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores. - Luca Bertaccini; Matteo Perotti; Stefan Mach; Pasquale Davide Schiavone; Florian Zaruba; Luca Benini (ISCAS, 2021)

RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors. - Matteo Perotti; Giuseppe Tagliavini; Stefan Mach; Luca Bertaccini; Luca Benini (SAMOS, 2021)

A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design. - Matteo Perotti; Matheus A. Cavalcante; Nils Wistoff; Renzo Andri; Lukas Cavigelli; Luca Benini (ASAP, 2022)

Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training. - Angelo Garofalo; Matteo Perotti; Luca Valente; Yvan Tortorella; Alessandro Nadalini; Luca Benini; Davide Rossi; Francesco Conti 001 (ESSCIRC, 2022)

Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters. - Matheus A. Cavalcante; Domenic Wüthrich; Matteo Perotti; Samuel Riedel; Luca Benini (ICCAD, 2022)

AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads. - Chi Zhang; Paul Scheffler; Thomas Benz; Matteo Perotti; Luca Benini (DATE, 2023)

Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. - MohammadHossein AskariHemmat; Théo Dupuis; Yoan Fournier; Nizar El Zarif; Matheus A. Cavalcante; Matteo Perotti; Frank K. Gürkaynak; Luca Benini; François Leduc-Primeau; Yvon Savaria; Jean-Pierre David (ISCAS, 2023)

DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training. - Angelo Garofalo; Yvan Tortorella; Matteo Perotti; Luca Valente; Alessandro Nadalini; Luca Benini; Davide Rossi; Francesco Conti 001 (CoRR, 2023)

Ara2: Exploring Single- and Multi-Core Vector Processing with an Efficient RVV1.0 Compliant Open-Source Processor. - Matteo Perotti; Matheus A. Cavalcante; Renzo Andri; Lukas Cavigelli; Luca Benini (CoRR, 2023)

Stella Nera: Achieving 161 TOp/s/W with Multiplier-free DNN Acceleration based on Approximate Matrix Multiplication. - Jannis Schönleber; Lukas Cavigelli; Renzo Andri; Matteo Perotti; Luca Benini (CoRR, 2023)

Yun: An Open-Source, 64-Bit RISC-V-Based Vector Processor With Multi-Precision Integer and Floating-Point Support in 65-nm CMOS. - Matteo Perotti; Matheus A. Cavalcante; Alessandro Ottaviano; Jiantao Liu; Luca Benini (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads. - Matteo Perotti; Michele Raeber; Mattia Sinigaglia; Matheus A. Cavalcante; Davide Rossi; Luca Benini (ASAP, 2024)

MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication. - Matteo Perotti; Yichao Zhang 003; Matheus A. Cavalcante; Enis Mustafa; Luca Benini (DATE, 2024)

Near-Memory Parallel Indexing and Coalescing: Enabling Highly Efficient Indirect Access for SpMV. - Chi Zhang; Paul Scheffler; Thomas Benz; Matteo Perotti; Luca Benini (DATE, 2024)

SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications. - Michael Rogenmoser; Alessandro Ottaviano; Thomas Benz; Robert Balas; Matteo Perotti; Angelo Garofalo; Luca Benini (CoRR, 2024)

Ara2: Exploring Single- and Multi-Core Vector Processing With an Efficient RVV 1.0 Compliant Open-Source Processor. - Matteo Perotti; Matheus A. Cavalcante; Renzo Andri; Lukas Cavigelli; Luca Benini (IEEE Trans. Computers, 2024)

Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications. - Danilo Cammarata; Matteo Perotti; Marco Bertuletti; Angelo Garofalo; Pasquale Davide Schiavone; David Atienza; Luca Benini (CF (Companion), 2025)

AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance. - Matteo Perotti; Vincenzo Maisto; Moritz Imfeld; Nils Wistoff; Alessandro Cilardo; Luca Benini (CF (Companion), 2025)

AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors. - Navaneeth Kunhi Purayil; Matteo Perotti; Tim Fischer 001; Luca Benini (DATE, 2025)

A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. - Angelo Garofalo; Alessandro Ottaviano; Matteo Perotti; Thomas Benz; Yvan Tortorella; Robert Balas; Michael Rogenmoser; Chi Zhang; Luca Bertaccini; Nils Wistoff; Maicol Ciani; Cyril Koenig; et al. (CoRR, 2025)

Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency. - Matteo Perotti; Samuel Riedel; Matheus A. Cavalcante; Luca Benini (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)