A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology. - Gautam R. Gangasani; Chun-Ming Hsu; John F. Bulzacchelli; Troy J. Beukema; William R. Kelly; Hui H. Xu; David Freitas; Andrea Prati 002; Daniele Gardellini; Robert Reutemann; Giovanni Cervelli; Juergen Hertle; et al. (IEEE J. Solid State Circuits, 2014)

A 1.1pJ/b/Lane, 1.8Tb/s Chiplet Over XSR-MCM Channels Using 113Gb/s PAM-4 Transceiver with Signal Equalization and Envelope Adaptation Using TX-FFE in 5nm CMOS. - Gautam R. Gangasani; A. Mostafa; A. Singh; Daniel W. Storaska; D. Prabakaran; K. Mohammad; Matthew Baecher; M. Shannon; Michael Sorna; Michael Wielgos; P. Jenkins; P. B. Ramakrishna; et al. (VLSI Technology and Circuits, 2024)