Millimeter-scale nearly perpetual sensor system with stacked battery and solar cells. - Gregory K. Chen; Matthew Fojtik; Daeyeon Kim; David Fick; Junsun Park; Mingoo Seok; Mao-Ter Chen; Zhiyoong Foo; Dennis Sylvester; David T. Blaauw (ISSCC, 2010)

In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter. - David Fick; Nurrachman Liu; Zhiyoong Foo; Matthew Fojtik; Jae-sun Seo; Dennis Sylvester; David T. Blaauw (ISSCC, 2010)

Early detection of oxide breakdown through in situ degradation sensing. - Prashant Singh; Zhiyoong Foo; Michael Wieckowski; Scott Hanson; Matthew Fojtik; David T. Blaauw; Dennis Sylvester (ISSCC, 2010)

A 1.85fW/bit ultra low leakage 10T SRAM with speed compensation scheme. - Daeyeon Kim; Gregory K. Chen; Matthew Fojtik; Mingoo Seok; David T. Blaauw; Dennis Sylvester (ISCAS, 2011)

Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores. - David Fick; Ronald G. Dreslinski; Bharan Giridhar; Gyouho Kim; Sangwon Seo; Matthew Fojtik; Sudhir Satpathy; Yoonmyung Lee; Daeyeon Kim; Nurrachman Liu; Michael Wieckowski; Gregory K. Chen; et al. (ISSCC, 2012)

Bubble Razor: An architecture-independent approach to timing-error detection and correction. - Matthew Fojtik; David Fick; Yejoong Kim; Nathaniel Ross Pinckney; David Money Harris; David T. Blaauw; Dennis Sylvester (ISSCC, 2012)

A 2.98nW bandgap voltage reference using a self-tuning low leakage sample and hold. - Yen-Po Chen; Matthew Fojtik; David T. Blaauw; Dennis Sylvester (VLSIC, 2012)

Pulse amplification based dynamic synchronizers with metastability measurement using capacitance de-rating. - Bharan Giridhar; Matthew Fojtik; David Fick; Dennis Sylvester; David T. Blaauw (CICC, 2013)

Centip3De: a many-core prototype exploring 3D integration and near-threshold computing. - Ronald G. Dreslinski; David Fick; Bharan Giridhar; Gyouho Kim; Sangwon Seo; Matthew Fojtik; Sudhir Satpathy; Yoonmyung Lee; Daeyeon Kim; Nurrachman Liu; Michael Wieckowski; Gregory K. Chen; et al. (Commun. ACM, 2013)

Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS. - David Fick; Ronald G. Dreslinski; Bharan Giridhar; Gyouho Kim; Sangwon Seo; Matthew Fojtik; Sudhir Satpathy; Yoonmyung Lee; Daeyeon Kim; Nurrachman Liu; Michael Wieckowski; Gregory K. Chen; et al. (IEEE J. Solid State Circuits, 2013)

Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction. - Matthew Fojtik; David Fick; Yejoong Kim; Nathaniel Ross Pinckney; David Money Harris; David T. Blaauw; Dennis Sylvester (IEEE J. Solid State Circuits, 2013)

A Millimeter-Scale Energy-Autonomous Sensor System With Stacked Battery and Solar Cells. - Matthew Fojtik; Daeyeon Kim; Gregory K. Chen; Yu-Shiang Lin; David Fick; Junsun Park; Mingoo Seok; Mao-Ter Chen; Zhiyoong Foo; David T. Blaauw; Dennis Sylvester (IEEE J. Solid State Circuits, 2013)

Centip3De: A 64-Core, 3D Stacked Near-Threshold System. - Ronald G. Dreslinski; David Fick; Bharan Giridhar; Gyouho Kim; Sangwon Seo; Matthew Fojtik; Sudhir Satpathy; Yoonmyung Lee; Daeyeon Kim; Nurrachman Liu; Michael Wieckowski; Gregory K. Chen; et al. (IEEE Micro, 2013)

A Pausible Bisynchronous FIFO for GALS Systems. - Ben Keller; Matthew Fojtik; Brucek Khailany (ASYNC, 2015)

Modeling and Analysis of Power Supply Noise Tolerance with Fine-Grained GALS Adaptive Clocks. - Divya Akella Kamakshi; Matthew Fojtik; Brucek Khailany; Sudhir S. Kudva; Yaping Zhou; Benton H. Calhoun (ASYNC, 2016)

8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring. - John M. Wilson 002; Matthew R. Fojtik; John W. Poulton; Xi Chen 033; Stephen G. Tell; Thomas H. Greer; C. Thomas Gray; William J. Dally (ISSCC, 2016)

A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation. - Mahmut E. Sinangil; John W. Poulton; Matthew R. Fojtik; Thomas H. Greer; Stephen G. Tell; Andreas J. Gotterba; Jesse Wang; Jason Golbus; Brian Zimmer; William J. Dally; C. Thomas Gray (IEEE J. Solid State Circuits, 2016)

Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects. - Walker J. Turner; John W. Poulton; John M. Wilson 002; Xi Chen 033; Stephen G. Tell; Matthew Fojtik; Thomas H. Greer; Brian Zimmer; Sanquan Song; Nikola Nedovic; Sudhir S. Kudva; Sunil R. Sudhakaran; et al. (CICC, 2018)

A modular digital VLSI flow for high-productivity SoC design. - Brucek Khailany; Evgeni Khmer; Rangharajan Venkatesan; Jason Clemons; Joel S. Emer; Matthew Fojtik; Alicia Klinefelter; Michael Pellauer; Nathaniel Ross Pinckney; Yakun Sophia Shao; Shreesha Srinath; Christopher Torng; et al. (DAC, 2018)

A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET. - Matthew Fojtik; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Stephen G. Tell; Brian Zimmer; Tezaswi Raja; Kevin Zhou; William J. Dally; Brucek Khailany (ASYNC, 2019)

A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. - Rangharajan Venkatesan; Yakun Sophia Shao; Brian Zimmer; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (Hot Chips Symposium, 2019)

MAGNet: A Modular Accelerator Generator for Neural Networks. - Rangharajan Venkatesan; Yakun Sophia Shao; Miaorong Wang; Jason Clemons; Steve Dai; Matthew Fojtik; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Yanqing Zhang 002; Brian Zimmer; et al. (ICCAD, 2019)

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. - Yakun Sophia Shao; Jason Clemons; Rangharajan Venkatesan; Brian Zimmer; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (MICRO, 2019)

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. - Brian Zimmer; Rangharajan Venkatesan; Yakun Sophia Shao; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (VLSI Circuits, 2019)

A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. - Brian Zimmer; Rangharajan Venkatesan; Yakun Sophia Shao; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (IEEE J. Solid State Circuits, 2020)

Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes. - Haoxing Ren; Matthew Fojtik (ASP-DAC, 2021)

Invited- NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning. - Haoxing Ren; Matthew Fojtik (DAC, 2021)

Simba: scaling deep-learning inference with chiplet-based architecture. - Yakun Sophia Shao; Jason Clemons; Rangharajan Venkatesan; Brian Zimmer; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (Commun. ACM, 2021)

NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning. - Haoxing Ren; Matthew Fojtik; Brucek Khailany (CoRR, 2021)

NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model. - Chia-Tung Ho; Alvin Ho; Matthew Fojtik; Minsoo Kim; Shang Wei; Yaguang Li; Brucek Khailany; Haoxing Ren (ISPD, 2023)

Machine Learning and Algorithms: Let Us Team Up for EDA. - Haoxing Ren; Brucek Khailany; Matthew Fojtik; Yanqing Zhang 002 (IEEE Des. Test, 2023)