An Architecture for Efficient Lisp List Access. - Andrew R. Pleszkun; Matthew Thazhuthaveetil (ISCA, 1986)

The Architecture of Lisp Machines. - Andrew R. Pleszkun; Matthew Thazhuthaveetil (Computer, 1987)

On the Structural Locality of Reference in LISP List Access Streams. - Matthew Thazhuthaveetil; Andrew R. Pleszkun (Inf. Process. Lett., 1987)

Hotspot Contention in Non-Blocking Multistage Interconnection Networks. - Robert L. Lesher; Matthew Thazhuthaveetil (ICPP (1), 1990)

A write update cache coherence protocol for MIN-based multiprocessors with accessibility-based split caches. - Mazin S. Algudady; Chita R. Das; Matthew Thazhuthaveetil (SC, 1990)

Dependability Modeling for Multiprocessors. - Chita R. Das; Jeffrey T. Kreulen; Matthew Thazhuthaveetil; Laxmi N. Bhuyan (Computer, 1990)

Application-dependent simulation of microprocessor-based multiprocessors. - Jeffrey T. Kreulen; Matthew J. Thazhuthaveetil (Microprocess. Microsystems, 1990)

A Cache-Based Checkpointing Scheme for MIN-Based Multiprocessors. - Mazin S. Algudady; Chita R. Das; Matthew Thazhuthaveetil (ICPP (1), 1991)

Effect of Hot Spots on Multiprocessor Systems Using Circuit Switched Interconnection Networks. - Lizyamma Kurian; Matthew Thazhuthaveetil (ICPP (1), 1991)

Parallel hough transform algorithm performance. - Matthew J. Thazhuthaveetil; Anish V. Shah (Image Vis. Comput., 1991)

A Cache Coherence Protocol for MIN-Based Multprocessors With Limited Inclusion. - Mazin S. Yousif; Chita R. Das; Matthew Thazhuthaveetil (ICPP (1), 1993)

Design of an MS-DOS PC program profiler. - K. V. Subramaniam; Matthew J. Thazhuthaveetil (Microprocess. Microsystems, 1994)

A Cache coherence protocol for MIN-based multiprocessors. - Mazin S. Yousif; Chita R. Das; Matthew J. Thazhuthaveetil (J. Supercomput., 1994)

Cache Coherence in Multiprocessors: A Survey. - Mazin S. Yousif; Matthew Thazhuthaveetil; Chita R. Das (Adv. Comput., 1995)

TWLinuX : Operating System Support for Optimistic Parallel Discrete Event Simulation. - Subramania Sharma; Matthew Thazhuthaveetil (HiPC, 2001)

A Programmable Hardware Path Profiler. - Kapil Vaswani; Matthew J. Thazhuthaveetil; Y. N. Srikant (CGO, 2005)

Offloading Bloom Filter Operations to Network Processor for Parallel Query Processing in Cluster of Workstations. - V. Santhosh Kumar; Matthew J. Thazhuthaveetil; R. Govindarajan (HiPC, 2005)

Construction and use of linear regression models for processor performance analysis. - P. J. Joseph; Kapil Vaswani; Matthew J. Thazhuthaveetil (HPCA, 2006)

Exploiting programmable network interfaces for parallel query execution in workstation clusters. - V. Santhosh Kumar; Matthew J. Thazhuthaveetil; R. Govindarajan (IPDPS, 2006)

A Predictive Performance Model for Superscalar Processors. - P. J. Joseph; Kapil Vaswani; Matthew J. Thazhuthaveetil (MICRO, 2006)

Microarchitecture Sensitive Empirical Models for Compiler Optimizations. - Kapil Vaswani; Matthew J. Thazhuthaveetil; Y. N. Srikant; P. J. Joseph (CGO, 2007)

Impact of message compression on the scalability of an atmospheric modeling application on clusters. - V. Santhosh Kumar; Ravi S. Nanjundiah; Matthew J. Thazhuthaveetil; R. Govindarajan (Parallel Comput., 2008)

Software Pipelined Execution of Stream Programs on GPUs. - Abhishek Udupa; R. Govindarajan; Matthew J. Thazhuthaveetil (CGO, 2009)

Synergistic execution of stream programs on multicores with accelerators. - Abhishek Udupa; R. Govindarajan; Matthew J. Thazhuthaveetil (LCTES, 2009)

Fast and efficient automatic memory management for GPUs using compiler-assisted runtime coherence scheme. - Sreepathi Pai; R. Govindarajan; Matthew J. Thazhuthaveetil (PACT, 2012)

CUDA-For-Clusters: A System for Efficient Execution of CUDA Kernels on Multi-core Clusters. - Raghu Prabhakar; R. Govindarajan; Matthew J. Thazhuthaveetil (Euro-Par, 2012)

Improving GPGPU concurrency with elastic kernels. - Sreepathi Pai; Matthew J. Thazhuthaveetil; R. Govindarajan (ASPLOS, 2013)

Preemptive thread block scheduling with online structural runtime prediction for concurrent GPGPU kernels. - Sreepathi Pai; R. Govindarajan; Matthew J. Thazhuthaveetil (PACT, 2014)

Tile Size and Loop Order Selection using Machine Learning for Multi-/Many-Core Architectures. - Shilpa Babalad; Shirish K. Shevade; Matthew Jacob Thazhuthaveetil; R. Govindarajan (ICS, 2024)