Optimal logarithmic adder structures with a fanout of two for minimizing the area-delay product. - Matthew M. Ziegler; Mircea Stan (ISCAS (2), 2001)

A Case for CMOS/nano co-design. - Matthew M. Ziegler; Mircea R. Stan (ICCAD, 2002)

The CMOS/nano interface from a circuits perspective. - Matthew M. Ziegler; Mircea R. Stan (ISCAS (4), 2003)

Molecular electronics: from devices and interconnect to circuits and architecture. - Mircea R. Stan; Paul D. Franzon; Seth Copen Goldstein; John C. Lach; Matthew M. Ziegler (Proc. IEEE, 2003)

A Unified Design Space for Regular Parallel Prefix Adders. - Matthew M. Ziegler; Mircea R. Stan (DATE, 2004)

Large-signal two-terminal device model for nanoelectronic circuit analysis. - Garrett S. Rose; Matthew M. Ziegler; Mircea R. Stan (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Hybrid CMOS/Molecular Electronic Circuits. - Mircea R. Stan; Garrett S. Rose; Matthew M. Ziegler (VLSI Design, 2006)

Structured and tuned array generation (STAG) for high-performance random logic. - Matthew M. Ziegler; Gary S. Ditlow; Stephen V. Kosonocky; Zhenyu Qi 001; Mircea R. Stan (ACM Great Lakes Symposium on VLSI, 2007)

Multi-Dimensional Circuit and Micro-Architecture Level Optimization. - Zhenyu Qi 001; Matthew M. Ziegler; Stephen V. Kosonocky; Jan M. Rabaey; Mircea R. Stan (ISQED, 2007)

A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing. - Azeez J. Bhavnagarwala; Stephen Kosonocky; Carl Radens; Yuen H. Chan; Kevin Stawiasz; Uma Srinivasan 002; Steven P. Kowalczyk; Matthew M. Ziegler (IEEE J. Solid State Circuits, 2008)

The opportunity cost of low power design: a case study in circuit tuning. - Matthew M. Ziegler; Victor V. Zyuban; George Gristede; Milena Vratonjic; Joshua Friedrich (ISLPED, 2009)

A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR). - Milena Vratonjic; Matthew M. Ziegler; George Gristede; Victor V. Zyuban; Thomas Mitchell; Ee Cho; Chandu Visweswariah; Vojin G. Oklobdzija (PATMOS, 2009)

LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs. - Minsik Cho; Hua Xiang 001; Haoxing Ren; Matthew M. Ziegler; Ruchir Puri (ICCAD, 2013)

Power reduction by aggressive synthesis design space exploration. - Matthew M. Ziegler; George Gristede; Victor V. Zyuban (ISLPED, 2013)

Network flow based datapath bit slicing. - Hua Xiang 001; Minsik Cho; Haoxing Ren; Matthew M. Ziegler; Ruchir Puri (ISPD, 2013)

POWER8 design methodology innovations for improving productivity and reducing power. - Matthew M. Ziegler; Ruchir Puri; Bob Philhower; Robert L. Franch; Wing K. Luk; Jens Leenstra; Peter Verwegen; Niels Fricke; George Gristede; Eric Fluhr; Victor V. Zyuban (CICC, 2014)

The POWER8TM processor: Designed for big data, analytics, and cloud environments. - Joshua Friedrich; Hung Q. Le; William J. Starke; Jeff Stuecheli; Balaram Sinharoy; Eric J. Fluhr; Daniel M. Dreps; Victor V. Zyuban; Gregory S. Still; Christopher J. Gonzalez; David Hogenmiller; Frank Malgioglio; et al. (ICICDT, 2014)

Bridging high performance and low power in processor design. - Ruchir Puri; Mihir R. Choudhury; Haifeng Qian; Matthew M. Ziegler (ISLPED, 2014)

5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth. - Eric J. Fluhr; Joshua Friedrich; Daniel M. Dreps; Victor V. Zyuban; Gregory S. Still; Christopher J. Gonzalez; Allen Hall; David Hogenmiller; Frank Malgioglio; Ryan Nett; Jose Paredes; Juergen Pille; et al. (ISSCC, 2014)

4.1 22nm Next-generation IBM System z microprocessor. - James D. Warnock; Brian W. Curran; John Badar; Gregory Fredeman; Donald W. Plass; Yuen H. Chan; Sean M. Carey; Gerard Salem; Friedrich Schroeder; Frank Malgioglio; Guenter Mayer; Christopher J. Berry; et al. (ISSCC, 2015)

14nm FinFET based supply voltage boosting techniques for extreme low Vmin operation. - Rajiv V. Joshi; Matthew M. Ziegler; Holger Wetter; C. Wandel; Herschel A. Ainspan (VLSIC, 2015)

IBM z13 circuit design and methodology. - James D. Warnock; Christopher J. Berry; Michael H. Wood; Leon J. Sigal; Yun-Chan Myung; Guenter Mayer; Mark D. Mayo; Y. Chan; Frank Malgioglio; Gerald Strevig; Charudhattan Nagarajan; Sean M. Carey; et al. (IBM J. Res. Dev., 2015)

IBM POWER8 circuit design and energy optimization. - Victor V. Zyuban; Joshua Friedrich; Daniel M. Dreps; Jürgen Pille; Donald W. Plass; Phillip J. Restle; Zeynep Toprak Deniz; Matthew M. Ziegler; Sam G. Chu; Md. Saiful Islam 004; James D. Warnock; Bob Philhower; et al. (IBM J. Res. Dev., 2015)

Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction. - Rajiv V. Joshi; Keunwoo Kim; Rouwaida Kanj; Ajay N. Bhoj; Matthew M. Ziegler; Phil Oldiges; Pranita Kerber; Robert Wong; Terence Hook; Sudesh Saroop; Carl Radens; Chun-Chen Yeh (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A synthesis-parameter tuning system for autonomous design-space exploration. - Matthew M. Ziegler; Hung-Yi Liu; George Gristede; Bruce Owens; Ricardo Nigaglioni; Luca P. Carloni (DATE, 2016)

A Scalable Black-Box Optimization System for Auto-Tuning VLSI Synthesis Programs. - Matthew M. Ziegler; Hung-Yi Liu; George Gristede; Bruce Owens; Ricardo Nigaglioni; Luca P. Carloni (RES4ANT@DATE, 2016)

Scalable Auto-Tuning of Synthesis Parameters for Optimizing High-Performance Processors. - Matthew M. Ziegler; Hung-Yi Liu; Luca P. Carloni (ISLPED, 2016)

Early Scenario Pruning for Efficient Design Space Exploration in Physical Synthesis. - Mohd Anwar; Sourav Saha; Matthew M. Ziegler; Lakshmi N. Reddy (VLSID, 2016)

Programmable supply boosting techniques for near threshold and wide operating voltage SRAM. - Rajiv V. Joshi; Matthew M. Ziegler (CICC, 2017)

Very Low Voltage (VLV) Design. - Ramon Bertran; Pradip Bose; David M. Brooks; Jeff Burns; Alper Buyuktosunoglu; Nandhini Chandramoorthy; Eric Cheng; Martin Cochet; Schuyler Eldridge; Daniel Friedman; Hans M. Jacobson; Rajiv V. Joshi; et al. (ICCD, 2017)

Machine learning techniques for taming the complexity of modern hardware design. - Matthew M. Ziegler; Ramon Bertran Monfort; Alper Buyuktosunoglu; Pradip Bose (IBM J. Res. Dev., 2017)

A Low Voltage SRAM Using Resonant Supply Boosting. - Rajiv V. Joshi; Matthew M. Ziegler; Holger Wetter (IEEE J. Solid State Circuits, 2017)

Cascaded and resonant SRAM supply boosting for ultra-low voltage cognitive IoT applications. - Rajiv V. Joshi; Matthew M. Ziegler; Karthik Swaminathan; Nandhini Chandramoorthy (CICC, 2018)

Across the Stack Opportunities for Deep Learning Acceleration. - Vijayalakshmi Srinivasan; Bruce M. Fleischer; Sunil Shukla; Matthew M. Ziegler; Joel Silberman; Jinwook Oh; Jungwook Choi; Silvia M. Mueller; Ankur Agrawal; Tina Babinsky; Nianzheng Cao; Chia-Yu Chen; et al. (ISLPED, 2018)

A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference. - Bruce M. Fleischer; Sunil Shukla; Matthew M. Ziegler; Joel Silberman; Jinwook Oh; Vijayalakshmi Srinivasan; Jungwook Choi; Silvia M. Mueller; Ankur Agrawal; Tina Babinsky; Nianzheng Cao; Chia-Yu Chen; et al. (VLSI Circuits, 2018)

A Learning-Based Recommender System for Autotuning Design Flows of Industrial High-Performance Processors. - Jihye Kwon; Matthew M. Ziegler; Luca P. Carloni (DAC, 2019)

Resilient Low Voltage Accelerators for High Energy Efficiency. - Nandhini Chandramoorthy; Karthik Swaminathan; Martin Cochet; Arun Paidimarri; Schuyler Eldridge; Rajiv V. Joshi; Matthew M. Ziegler; Alper Buyuktosunoglu; Pradip Bose (HPCA, 2019)

Low Power Design From Moore to AI for nm Era : Invited Paper. - Rajiv V. Joshi; Matthew M. Ziegler (MIXDES, 2019)

Conference Report from the 2019 International Symposium on Low Power Electronics and Design (ISLPED). - Andreas Burg 001; Matthew M. Ziegler; Saibal Mukhopdhyay (IEEE Des. Test, 2019)

Research From the IEEE IBM AI Compute and Emerging Technology Symposia. - Matthew M. Ziegler; Krishnan Kailas; Xin Zhang 025; Rajiv V. Joshi (IEEE J. Emerg. Sel. Topics Circuits Syst., 2019)

A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference. - Jinwook Oh; Sae Kyu Lee; Mingu Kang; Matthew M. Ziegler; Joel Silberman; Ankur Agrawal; Swagath Venkataramani; Bruce M. Fleischer; Michael Guillorn; Jungwook Choi; Wei Wang 333; Silvia M. Mueller; et al. (VLSI Circuits, 2020)

Efficient AI System Design With Cross-Layer Approximate Computing. - Swagath Venkataramani; Xiao Sun 013; Naigang Wang; Chia-Yu Chen; Jungwook Choi; Mingu Kang; Ankur Agarwal; Jinwook Oh; Shubham Jain; Tina Babinsky; Nianzheng Cao; Thomas W. Fox; et al. (Proc. IEEE, 2020)

Online and Offline Machine Learning for Industrial Design Flow Tuning: (Invited - ICCAD Special Session Paper). - Matthew M. Ziegler; Jihye Kwon; Hung-Yi Liu; Luca P. Carloni (ICCAD, 2021)

RaPiD: AI Accelerator for Ultra-low Precision Training and Inference. - Swagath Venkataramani; Vijayalakshmi Srinivasan; Wei Wang 333; Sanchari Sen; Jintao Zhang; Ankur Agrawal; Monodeep Kar; Shubham Jain; Alberto Mannari; Hoang Tran; Yulong Li; Eri Ogawa; et al. (ISCA, 2021)

A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling. - Ankur Agrawal; Sae Kyu Lee; Joel Silberman; Matthew M. Ziegler; Mingu Kang; Swagath Venkataramani; Nianzheng Cao; Bruce M. Fleischer; Michael Guillorn; Matt Cohen; Silvia M. Mueller; Jinwook Oh; et al. (ISSCC, 2021)

Hyper-parameter Tuning for Progressive Learning and its Application to Network Cyber Security. - Rupesh Raj Karn; Matthew M. Ziegler; Jinwook Jung; Ibrahim Abe M. Elfadel (ISCAS, 2022)

Design Flow Parameter Optimization with Multi-Phase Positive Nondeterministic Tuning. - Matthew M. Ziegler; Lakshmi N. Reddy; Robert L. Franch (ISPD, 2022)

A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling. - Sae Kyu Lee; Ankur Agrawal; Joel Silberman; Matthew M. Ziegler; Mingu Kang; Swagath Venkataramani; Nianzheng Cao; Bruce M. Fleischer; Michael Guillorn; Matthew Cohen; Silvia M. Mueller; Jinwook Oh; et al. (IEEE J. Solid State Circuits, 2022)

14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (ISSCC, 2024)

Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (IEEE J. Solid State Circuits, 2025)