Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip. - Jin Ouyang; Jing Xie 006; Matthew Poremba; Yuan Xie 001 (ICCAD, 2010)

NVMain: An Architectural-Level Main Memory Simulator for Emerging Non-volatile Memories. - Matthew Poremba; Yuan Xie 001 (ISVLSI, 2012)

TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network. - Yuan-Ying Chang; Yoshi Shih-Chieh Huang; Matthew Poremba; Vijaykrishnan Narayanan; Yuan Xie 001; Chung-Ta King (HPCA, 2013)

A cost benefit analysis: The impact of defect clustering on the necessity of pre-bond tests. - Qiaosha Zou; Matt Poremba; Yuan Xie 001 (3DIC, 2014)

Designing vertical bandwidth reconfigurable 3D NoCs for many core systems. - Qiaosha Zou; Jia Zhan; Fen Ge; Matt Poremba; Yuan Xie 001 (3DIC, 2014)

NoΔ: Leveraging delta compression for end-to-end memory access in NoC based multicores. - Jia Zhan; Matthew Poremba; Yi Xu; Yuan Xie 001 (ASP-DAC, 2014)

CREAM: A Concurrent-Refresh-Aware DRAM Memory architecture. - Tao Zhang 032; Matthew Poremba; Cong Xu; Guangyu Sun 003; Yuan Xie 001 (HPCA, 2014)

EECache: exploiting design choices in energy-efficient last-level caches for chip multiprocessors. - Hsiang-Yun Cheng; Matthew Poremba; Narges Shahidi; Ivan Stalev; Mary Jane Irwin; Mahmut T. Kandemir; Jack Sampson; Yuan Xie 001 (ISLPED, 2014)

Heterogeneous architecture design with emerging 3D and non-volatile memory technologies. - Qiaosha Zou; Matthew Poremba; Rui He; Wei Yang; Junfeng Zhao 003; Yuan Xie 001 (ASP-DAC, 2015)

DESTINY: a tool for modeling emerging 3D NVM and eDRAM caches. - Matt Poremba; Sparsh Mittal; Dong Li 001; Jeffrey S. Vetter; Yuan Xie 001 (DATE, 2015)

NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems. - Matthew Poremba; Tao Zhang 032; Yuan Xie 001 (IEEE Comput. Archit. Lett., 2015)

EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors. - Hsiang-Yun Cheng; Matt Poremba; Narges Shahidi; Ivan Stalev; Mary Jane Irwin; Mahmut T. Kandemir; Jack Sampson; Yuan Xie 001 (ACM Trans. Archit. Code Optim., 2015)

Fine-granularity tile-level parallelism in non-volatile memory architecture with two-dimensional bank subdivision. - Matthew Poremba; Tao Zhang 032; Yuan Xie 001 (DAC, 2016)

Efficient synthetic traffic models for large, complex SoCs. - Jieming Yin; Onur Kayiran; Matthew Poremba; Natalie D. Enright Jerger; Gabriel H. Loh (HPCA, 2016)

Design and Analysis of an APU for Exascale Computing. - Thiruvengadam Vijayaraghavan; Yasuko Eckert; Gabriel H. Loh; Michael J. Schulte; Mike Ignatowski; Bradford M. Beckmann; William C. Brantley; Joseph L. Greathouse; Wei Huang 004; Arun Karunanithi; Onur Kayiran; Mitesh R. Meswani; et al. (HPCA, 2017)

There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes. - Matthew Poremba; Itir Akgun; Jieming Yin; Onur Kayiran; Yuan Xie 001; Gabriel H. Loh (ISCA, 2017)

Lost in Abstraction: Pitfalls of Analyzing GPUs at the Intermediate Language Level. - Anthony Gutierrez; Bradford M. Beckmann; Alexandru Dutu; Joseph Gross; Michael LeBeane; John Kalamatianos; Onur Kayiran; Matthew Poremba; Brandon Potter; Sooraj Puthoor; Matthew D. Sinclair; Mark Wyse; et al. (HPCA, 2018)

Modular Routing Design for Chiplet-Based Systems. - Jieming Yin; Zhifeng Lin; Onur Kayiran; Matthew Poremba; Muhammad Shoaib Bin Altaf; Natalie D. Enright Jerger; Gabriel H. Loh (ISCA, 2018)

A Research Retrospective on AMD's Exascale Computing Journey. - Gabriel H. Loh; Michael J. Schulte; Mike Ignatowski; Vignesh Adhinarayanan; Shaizeen Aga; Derrick Aguren; Varun Agrawal; Ashwin M. Aji; Johnathan Alsop; Paul T. Bauman; Bradford M. Beckmann; Majed Valad Beigi; et al. (ISCA, 2023)