Increasing the number of effective registers in a low-power processor using a windowed register file. - Rajiv A. Ravindran; Robert M. Senger; Eric D. Marsman; Ganesh S. Dasika; Matthew R. Guthaus; Scott A. Mahlke; Richard B. Brown (CASES, 2003)

A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference. - Robert M. Senger; Eric D. Marsman; Michael S. McCorquodale; Fadi H. Gebara; Keith L. Kraver; Matthew R. Guthaus; Richard B. Brown (DAC, 2003)

Optimization objectives and models of variation for statistical gate sizing. - Matthew R. Guthaus; Natesan Venkateswaran; Vladimir Zolotov; Dennis Sylvester; Richard B. Brown (ACM Great Lakes Symposium on VLSI, 2005)

Gate sizing using incremental parameterized statistical timing analysis. - Matthew R. Guthaus; Natesan Venkateswaran; Chandu Visweswariah; Vladimir Zolotov (ICCAD, 2005)

Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor. - Rajiv A. Ravindran; Robert M. Senger; Eric D. Marsman; Ganesh S. Dasika; Matthew R. Guthaus; Scott A. Mahlke; Richard B. Brown (IEEE Trans. Computers, 2005)

Process-induced skew reduction in nominal zero-skew clock trees. - Matthew R. Guthaus; Dennis Sylvester; Richard B. Brown (ASP-DAC, 2006)

Clock buffer and wire sizing using sequential programming. - Matthew R. Guthaus; Dennis Sylvester; Richard B. Brown (DAC, 2006)

Clock tree analysis and synthesis considering process parameters and variability. - Matthew R. Guthaus (2006)

Clock tree synthesis with data-path sensitivity matching. - Matthew R. Guthaus; Dennis Sylvester; Richard B. Brown (ASP-DAC, 2008)

Measuring and modeling variabilityusing low-cost FPGAs. - Michael Brown; Cyrus Bazeghi; Matthew R. Guthaus; Jose Renau (FPGA, 2009)

Fault-tolerant synthesis using non-uniform redundancy. - Keven L. Woo; Matthew R. Guthaus (ICCD, 2009)

Teaching VLSI design in 10 weeks. - Matthew R. Guthaus (MSE, 2009)

Non-uniform clock mesh optimization with linear programming buffer insertion. - Matthew R. Guthaus; Gustavo Wilke; Ricardo Reis 001 (DAC, 2010)

Analysis of power supply induced jitter in actively de-skewed multi-core systems. - Derek Chan; Matthew R. Guthaus (ISQED, 2010)

Analysis of high-performance clock networks with RLC and transmission line effects. - Walter James Condley; Xuchu Hu; Matthew R. Guthaus (SLIP, 2010)

Clock tree optimization for Electromagnetic Compatibility (EMC). - Xuchu Hu; Matthew R. Guthaus (ASP-DAC, 2011)

Distributed Resonant clOCK grid Synthesis (ROCKS). - Xuchu Hu; Matthew R. Guthaus (DAC, 2011)

Leakage-aware redundancy for reliable sub-threshold memories. - Seokjoong Kim; Matthew R. Guthaus (DAC, 2011)

A methodology for local resonant clock synthesis using LC-assisted local clock buffers. - Walter James Condley; Xuchu Hu; Matthew R. Guthaus (ICCAD, 2011)

Low-power multiple-bit upset tolerant memory optimization. - Seokjoong Kim; Matthew R. Guthaus (ICCAD, 2011)

Distributed LC resonant clock tree synthesis. - Matthew R. Guthaus (ISCAS, 2011)

Package-chip co-design to increase flip-chip C4 reliability. - Sheldon Logan; Matthew R. Guthaus (ISQED, 2011)

Advanced logic design through hands-on digital music synthesis. - Walter James Condley; Andrew W. Hill; Matthew R. Guthaus (MSE, 2011)

SNM-aware power reduction and reliability improvement in 45nm SRAMs. - Seokjoong Kim; Matthew R. Guthaus (VLSI-SoC, 2011)

Library-aware resonant clock synthesis (LARCS). - Xuchu Hu; Walter James Condley; Matthew R. Guthaus (DAC, 2012)

Lithography-aware layout compaction. - Curtis Andrus; Matthew R. Guthaus (ACM Great Lakes Symposium on VLSI, 2012)

High-Performance, Low-Power Resonant Clocking: Embedded tutorial. - Matthew R. Guthaus; Baris Taskin (ICCAD, 2012)

VAR-TX: A variability-aware SRAM model for predicting the optimum architecture to achieve minimum access-time for yield enhancement in nano-scaled CMOS. - Jeren Samandari-Rad; Matthew R. Guthaus; Richard Hughey (ISQED, 2012)

Architecture for increased address space in an ultra-low-power microprocessor. - Bennion Redd; Spencer S. Kellis; Nathaniel Gaskin; Matthew Guthaus; Richard Brown 003 (MWSCAS, 2012)

Welcome from the general chair. - Matthew R. Guthaus (VLSI-SoC, 2012)

Dynamic voltage scaling for SEU-tolerance in low-power memories. - Seokjoong Kim; Matthew R. Guthaus (VLSI-SoC, 2012)

SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture. - Seokjoong Kim; Matthew R. Guthaus (VLSI-SoC (Selected Papers), 2012)

A single-VDD ultra-low energy sub-threshold FPGA. - Rajsaktish Sankaranarayanan; Matthew R. Guthaus (VLSI-SoC, 2012)

Harmonic resonant clocking. - Haven Blake Skinner; Xuchu Hu; Matthew R. Guthaus (VLSI-SoC, 2012)

Distributed LC Resonant Clock Grid Synthesis. - Xuchu Hu; Matthew R. Guthaus (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

High-performance clock mesh optimization. - Matthew R. Guthaus; Xuchu Hu; Gustavo Wilke; Guilherme Flach; Ricardo Reis 001 (ACM Trans. Design Autom. Electr. Syst., 2012)

Redundant C4 power pin placement to ensure robust power grid delivery. - Sheldon Logan; Matthew R. Guthaus (MWSCAS, 2013)

A decap placement methodology for reducing joule heating and temperature in PSN interconnect. - Sheldon Logan; Matthew R. Guthaus (MWSCAS, 2013)

Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors. - Janusz Rajski; Miodrag Potkonjak; Adit D. Singh; Abhijit Chatterjee; Zain Navabi; Matthew R. Guthaus; Sezer Gören 001 (VLSI-SoC, 2013)

Revisiting automated physical synthesis of high-performance clock networks. - Matthew R. Guthaus; Gustavo Wilke; Ricardo Reis 001 (ACM Trans. Design Autom. Electr. Syst., 2013)

Current-mode clock distribution. - Riadul Islam; Matthew R. Guthaus (ISCAS, 2014)

Confronting the Variability Issues Affecting the Performance of Next-Generation SRAM Design to Optimize and Predict the Speed and Yield. - Jeren Samandari-Rad; Matthew R. Guthaus; Richard Hughey (IEEE Access, 2014)

Switched capacitor quasi-adiabatic clocks. - Hany Ahmed Fahmy; Ping-Yao Lin; Riadul Islam; Matthew R. Guthaus (ISCAS, 2015)

Multi-frequency resonant clocks. - Benjamin M. LaCara; Ping-Yao Lin; Matthew R. Guthaus (ISCAS, 2015)

LC resonant clock resource minimization using compensation capacitance. - Ping-Yao Lin; Hany Ahmed Fahmy; Riadul Islam; Matthew R. Guthaus (ISCAS, 2015)

Differential current-mode clock distribution. - Riadul Islam; Hany Ahmed Fahmy; Ping-Yao Lin; Matthew R. Guthaus (MWSCAS, 2015)

Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop. - Riadul Islam; Matthew R. Guthaus (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

OpenRAM: an open-source memory compiler. - Matthew R. Guthaus; James E. Stine; Samira Ataei; Brian Chen; Bin Wu; Mehedi Sarwar (ICCAD, 2016)

A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS. - Samira Ataei; James E. Stine; Matthew R. Guthaus (ICCD, 2016)

Energy Savings and Performance Improvement in Subthreshold Using Adaptive Body Bias. - Rajsaktish Sankaranarayanan; Matthew R. Guthaus (ACM Great Lakes Symposium on VLSI, 2017)

Timing speculative SRAM. - Elnaz Ebrahimi 001; Matthew R. Guthaus; Jose Renau (ISCAS, 2017)

Architectural opportunities for novel dynamic EMI shifting (DEMIS). - Daphne I. Gorman; Matthew R. Guthaus; Jose Renau (MICRO, 2017)

CMCS: Current-Mode Clock Synthesis. - Riadul Islam; Matthew R. Guthaus (IEEE Trans. Very Large Scale Integr. Syst., 2017)

DCMCS: Highly Robust Low-Power Differential Current-Mode Clocking and Synthesis. - Riadul Islam; Hany Ahmed Fahmy; Ping-Yao Lin; Matthew R. Guthaus (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Fast and Area-Efficient SRAM Word-Line Optimization. - Bin Wu; James E. Stine; Matthew R. Guthaus (ISCAS, 2019)

Automated Synthesis of Multi-Port Memories and Control. - Hunter Nichols; Michael Grimes; Jennifer Sowash; Jesse Cirimelli-Low; Matthew R. Guthaus (VLSI-SoC, 2019)

Bottom-Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization. - Bin Wu; Matthew R. Guthaus (VLSI-SoC, 2019)

HCDN: Hybrid-Mode Clock Distribution Networks. - Riadul Islam; Matthew R. Guthaus (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

SRAM Design with OpenRAM in SkyWater 130nm. - Jesse Cirimelli-Low; Muhammad Hadir Khan; Samuel Crow; Amogh Lonkar; Bugra Onal; Andrew D. Zonenberg; Matthew R. Guthaus (ISCAS, 2023)

OpenSpike: An OpenRAM SNN Accelerator. - Farhad Modaresi; Matthew Guthaus; Jason K. Eshraghian (ISCAS, 2023)

NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report. - Matthew Guthaus; Christopher Batten; Erik Brunvand; Pierre-Emmanuel Gaillardon; David M. Harris; Rajit Manohar; Pinaki Mazumder; Larry T. Pileggi; James E. Stine (CoRR, 2023)

GAT-Steiner: Rectilinear Steiner Minimal Tree Prediction Using GNNs. - Bugra Onal; Eren Dogan; Muhammad Hadir Khan; Matthew R. Guthaus (ICCAD, 2024)

VLSI Hypergraph Partitioning with Deep Learning. - Muhammad Hadir Khan; Bugra Onal; Eren Dogan; Matthew R. Guthaus (CoRR, 2024)

Open-Source Silicon - Unleashing Innovation and Collaboration. - Matthew Guthaus; Kwantae Kim; Francisco A. Brito-Filho; Satoshi Kawakami; Boris Murmann (IEEE Des. Test, 2024)

Invited: Mapping Two Decades of Innovation: Lessons from 25 Years of ISPD Research. - Gona Rahmaniani; Matthew Guthaus; Laleh Behjat (ISPD, 2025)

Effective Capacitance Modeling Using Graph Neural Networks. - Eren Dogan; Matthew R. Guthaus (CoRR, 2025)

GATMesh: Clock Mesh Timing Analysis using Graph Neural Networks. - Muhammad Hadir Khan; Matthew Guthaus (CoRR, 2025)

OpenGCRAM: An Open-Source Gain Cell Compiler Enabling Design-Space Exploration for AI Workloads. - Xinxin Wang; Lixian Yan; Shuhan Liu; Luke Upton; Zhuoqi Cai; Yiming Tan; Shengman Li; Koustav Jana; Peijing Li; Jesse Cirimelli-Low; Thierry Tambe; Matthew Guthaus; et al. (CoRR, 2025)