Numerical modeling of advanced semiconductor devices. - Wai Lee; Steven E. Laux; Massimo V. Fischetti; Giorgio Baccarani; Antonio Gnudi; Johannes M. C. (Hans) Stork; Jack A. Mandelman; Emmanuel F. Crabbé; Matthew R. Wordeman; Farouk Odeh (IBM J. Res. Dev., 1992)

A half-micron CMOS logic generation. - Charles W. Koburger III; William F. Clark; James W. Adkisson; Eric Adler; Paul E. Bakeman; Albert S. Bergendahl; Alan B. Botula; W. Chang; Bijan Davari; John H. Givens; Howard H. Hansen; Steven J. Holmes; et al. (IBM J. Res. Dev., 1995)

Fault-tolerant designs for 256 Mb DRAM. - Toshiaki Kirihata; Yohji Watanabe; Hing Wong; John K. DeBrosse; Munehiro Yoshida; Daisuke Kato; Shuso Fujii; Matthew R. Wordeman; Peter Poechmueller; Stephen A. Parke; Yoshiaki Asao (IEEE J. Solid State Circuits, 1996)

A 286 mm2 256 Mb DRAM with ×32 both-ends DQ. - Yohji Watanabe; Ring Wong; Toshiaki Kirihata; Daisuke Kato; John K. DeBrosse; Takahiko Rara; Munehiro Yoshida; Rideo Mukai; Khandker N. Quader; Takeshi Nagai; Peter Poechmueller; Peter Pfefferl; et al. (IEEE J. Solid State Circuits, 1996)

Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. - W. K. Luk; Yasunao Katayama; Wei Hwang; Matthew R. Wordeman; Toshiaki Kirihata; Akashi Satoh; Seiji Munetoh; Hing Wong; B. El-Kareh; P. Xiao; Rajiv V. Joshi (ICCD, 1997)

Flexible test mode approach for 256-Mb DRAM. - Toshiaki Kirihata; Hing Wong; John K. DeBrosse; Yohji Watanabe; Takahiko Hara; Munehiro Yoshida; Matthew R. Wordeman; Shuso Fujii; Yoshiaki Asao; Bo Krsnik (IEEE J. Solid State Circuits, 1997)

A 220-mm2, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture. - Toshiaki Kirihata; Martin Gall; Kohji Hosokawa; Jean-Marc Dortu; Hing Wong; Peter Pfefferl; Brian L. Ji; Oliver Weinfurtner; John K. DeBrosse; Hartmud Terletzki; Manfred Selz; Wayne Ellis; et al. (IEEE J. Solid State Circuits, 1998)

A 390-mm2, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture. - Toshiaki Kirihata; Gerhard Mueller; Brian Ji; Gerd Frankowsky; Joseph M. Ross; Hartmud Terletzki; Dmitry G. Netis; Oliver Weinfurtner; David R. Hanson; Gabriel Daniel; Louis Lu-Chen Hsu; Daniel W. Storaska; et al. (IEEE J. Solid State Circuits, 1999)

A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs. - Heinz Hoenigschmid; Alexander Frey; John K. DeBrosse; Toshiaki Kirihata; Gerhard Mueller; Daniel W. Storaska; Gabriel Daniel; Gerd Frankowsky; Kevin P. Guay; David R. Hanson; Louis Lu-Chen Hsu; Brian Ji; et al. (IEEE J. Solid State Circuits, 2000)

1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro. - Osamu Takahashi; Sang H. Dhong; Manabu Ohkubo; Shohji Onishi; Robert H. Dennard; Robert Hannon; Scott Crowder; Subramanian S. Iyer; Matthew R. Wordeman; Bijan Davari; William B. Weinberger; Naoaki Aoki (IEEE J. Solid State Circuits, 2000)

An 800-MHz embedded DRAM with a concurrent refresh mode. - Toshiaki Kirihata; Paul C. Parries; David R. Hanson; Hoki Kim; John Golz; Gregory Fredeman; Raj Rajeevakumar; John Griesemer; Norman Robson; Alberto Cestero; Babar A. Khan; Geng Wang; et al. (IEEE J. Solid State Circuits, 2005)

Wafer-level 3D integration technology. - Steven J. Koester; Albert M. Young; Roy R. Yu; Sampath Purushothaman; Kuan-Neng Chen; Douglas C. La Tulipe Jr.; Narender Rana; Leathen Shi; Matthew R. Wordeman; Edmund J. Sprogis (IBM J. Res. Dev., 2008)

A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias. - Matt Wordeman; Joel Silberman; Gary W. Maier; Michael Scheuermann (ISSCC, 2012)

A shorted global clock design for multi-GHz 3D stacked chips. - Liang-Teck Pang; Phillip J. Restle; Matthew R. Wordeman; Joel A. Silberman; Robert L. Franch; Gary W. Maier (VLSIC, 2012)

Thermal analysis of multi-layer functional 3D logic stacks. - Michael Scheuermann; Shurong Tian; Raphael Robertazzi; Matthew R. Wordeman; C. Bergeron; H. Jacobson; Phillip J. Restle; Joel Silberman; Christy Tyberg (3DIC, 2016)

Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias. - Toshiaki Kirihata; John Golz; Matthew R. Wordeman; Pooja Batra; Gary W. Maier; Norman Robson; Troy L. Graves-abe; Daniel Berger; Subramanian S. Iyer (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

Analytical test of 3D integrated circuits. - Raphael Robertazzi; Micheal Scheurman; Matt Wordeman; Shurong Tian; Christy Tyberg (ITC, 2017)