A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation. - Chun-Ming Hsu; Matthew Z. Straayer; Michael H. Perrott (ISSCC, 2008)

A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance. - Belal Helal; Matthew Z. Straayer; Gu-Yeon Wei; Michael H. Perrott (IEEE J. Solid State Circuits, 2008)

A Low-Noise Wide-BW 3.6-GHz Digital ΔΣ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation. - Chun-Ming Hsu; Matthew Z. Straayer; Michael H. Perrott (IEEE J. Solid State Circuits, 2008)

A 12-Bit, 10-MHz Bandwidth, Continuous-Time ΣΔ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer. - Matthew Z. Straayer; Michael H. Perrott (IEEE J. Solid State Circuits, 2008)

Noise shaping techniques for analog and time to digital converters using voltage controlled oscillators. - Matthew Z. Straayer (2008)

A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping. - Matthew Z. Straayer; Michael H. Perrott (IEEE J. Solid State Circuits, 2009)

A 12b 200MS/s frequency scalable zero-crossing based pipelined ADC in 55nm CMOS. - Soon-Kyun Shin; Jacques Christophe Rudell; Denis C. Daly; Carlos E. Muñoz; Dong-Young Chang; Kush Gulati; Hae-Seung Lee; Matthew Z. Straayer (CICC, 2012)

11.6 A 21mW 15b 48MS/s zero-crossing pipeline ADC in 0.13μm CMOS with 74dB SNDR. - Dong-Young Chang; Carlos E. Muñoz; Denis C. Daly; Soon-Kyun Shin; Kevin Guay; Thomas Thurston; Hae-Seung Lee; Kush Gulati; Matthew Z. Straayer (ISSCC, 2014)

A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration. - Soon-Kyun Shin; Jacques Christophe Rudell; Denis C. Daly; Carlos E. Muñoz; Dong-Young Chang; Kush Gulati; Hae-Seung Lee; Matthew Z. Straayer (IEEE J. Solid State Circuits, 2014)

Session 15 overview: Data-converter techniques: Data converters subcommittee. - Seung-Tak Ryu; Matt Straayer (ISSCC, 2015)

EE3: Survey says! - Harry Lee; Matt Straayer; Chris Mangelsdorf (ISSCC, 2016)

27.5 A 4GS/s time-interleaved RF ADC in 65nm CMOS with 4GHz input bandwidth. - Matt Straayer; Jim Bales; Dwight Birdsall; Denis C. Daly; Phillip Elliott; Bill Foley; Roy Mason; Vikas Singh; Xuejin Wang (ISSCC, 2016)

EE6: Return of survey says! - Harry Lee; Matt Straayer; Chris Mangelsdorf (ISSCC, 2017)

Session 14 overview: High-resolution ADCs: Data converter subcommittee. - Matt Straayer; Seung-Tak Ryu; Un-Ku Moon (ISSCC, 2018)

Introduction to the Special Issue on the 2018 IEEE International Solid-State Circuits Conference (ISSCC). - Yong Ping Xu; Tai-Haur Kuo; Matt Straayer; Harish Krishnaswamy; Arun Natarajan 001 (IEEE J. Solid State Circuits, 2018)