Evaluating Thread Placement Based on Memory Access Patterns for Multi-core Processors. - Matthias Diener; Felipe Lopes Madruga; Eduardo Rocha Rodrigues; Marco A. Z. Alves; Jörg Schneider 001; Philippe Olivier Alexandre Navaux; Hans-Ulrich Heiss (HPCC, 2010)

Evaluating High Performance Computing on the Windows Azure Platform. - Eduardo Roloff; Francis Birck; Matthias Diener; Alexandre Carissimi; Philippe Olivier Alexandre Navaux (IEEE CLOUD, 2012)

High Performance Computing in the cloud: Deployment, performance and cost efficiency. - Eduardo Roloff; Matthias Diener; Alexandre Carissimi; Philippe Olivier Alexandre Navaux (CloudCom, 2012)

Using the Translation Lookaside Buffer to Map Threads in Parallel Applications Based on Shared Memory. - Eduardo Henrique Molina da Cruz; Matthias Diener; Philippe Olivier Alexandre Navaux (IPDPS, 2012)

Communication-Based Mapping Using Shared Pages. - Matthias Diener; Eduardo Henrique Molina da Cruz; Philippe Olivier Alexandre Navaux (IPDPS, 2013)

Analyzing resource interdependencies in multi-core architectures to improve scheduling decisions. - Anselm Busse; Jan Hendrik Schönherr; Matthias Diener; Gero Mühl; Jan Richling (SAC, 2013)

Energy Efficient Last Level Caches via Last Read/Write Prediction. - Marco A. Z. Alves; Carlos Villavieja; Matthias Diener; Philippe Olivier Alexandre Navaux (SBAC-PAD, 2013)

kMAF: automatic kernel-level management of thread and data affinity. - Matthias Diener; Eduardo Henrique Molina da Cruz; Philippe Olivier Alexandre Navaux; Anselm Busse; Hans-Ulrich Heiß (PACT, 2014)

Optimizing Memory Locality Using a Locality-Aware Page Table. - Eduardo Henrique Molina da Cruz; Matthias Diener; Marco A. Z. Alves; Laércio Lima Pilla; Philippe Olivier Alexandre Navaux (SBAC-PAD, 2014)

Dynamic thread mapping of shared memory applications by exploiting cache coherence protocols. - Eduardo Henrique Molina da Cruz; Matthias Diener; Marco A. Z. Alves; Philippe Olivier Alexandre Navaux (J. Parallel Distributed Comput., 2014)

Saving memory movements through vector processing in the DRAM. - Marco A. Z. Alves; Paulo C. Santos 001; Francis B. Moreira 001; Matthias Diener; Luigi Carro (CASES, 2015)

Locality and Balance for Communication-Aware Thread Mapping in Multicore Systems. - Matthias Diener; Eduardo Henrique Molina da Cruz; Marco A. Z. Alves; Mohammad S. Alhakeem; Philippe Olivier Alexandre Navaux; Hans-Ulrich Heiß (Euro-Par, 2015)

SiNUCA: A Validated Micro-Architecture Simulator. - Marco A. Z. Alves; Carlos Villavieja; Matthias Diener; Francis Birck Moreira; Philippe Olivier Alexandre Navaux (HPCC/CSS/ICESS, 2015)

Opportunities and Challenges of Performing Vector Operations inside the DRAM. - Marco A. Z. Alves; Paulo C. Santos 001; Matthias Diener; Luigi Carro (MEMSYS, 2015)

An Efficient Algorithm for Communication-Based Task Mapping. - Eduardo Henrique Molina da Cruz; Matthias Diener; Laércio Lima Pilla; Philippe Olivier Alexandre Navaux (PDP, 2015)

Locality vs. Balance: Exploring Data Mapping Policies on NUMA Systems. - Matthias Diener; Eduardo Henrique Molina da Cruz; Philippe Olivier Alexandre Navaux (PDP, 2015)

Reconfigurable Vector Extensions inside the DRAM. - Marco A. Z. Alves; Paulo C. Santos 001; Matthias Diener; Luigi Carro (ReCoSoC, 2015)

Partial coscheduling of virtual machines based on memory access patterns. - Anselm Busse; Jan Hendrik Schönherr; Matthias Diener; Philippe O. A. Navaux; Hans-Ulrich Heiß (SAC, 2015)

TABARNAC: visualizing and resolving memory access issues on NUMA architectures. - David Beniamine; Matthias Diener; Guillaume Huard; Philippe O. A. Navaux (VPA@SC, 2015)

Communication-aware thread mapping using the translation lookaside buffer. - Eduardo Henrique Molina da Cruz; Matthias Diener; Philippe O. A. Navaux (Concurr. Comput. Pract. Exp., 2015)

Communication-aware process and thread mapping using online communication detection. - Matthias Diener; Eduardo Henrique Molina da Cruz; Philippe Olivier Alexandre Navaux; Anselm Busse; Hans-Ulrich Heiß (Parallel Comput., 2015)

Characterizing communication and page usage of parallel applications for thread and data mapping. - Matthias Diener; Eduardo Henrique Molina da Cruz; Laércio Lima Pilla; Fabrice Dupros; Philippe Olivier Alexandre Navaux (Perform. Evaluation, 2015)

Automatic task and data mapping in shared memory architectures. - Matthias Diener (2015)

Performance Evaluation of Multiple Cloud Data Centers Allocations for HPC. - Eduardo Roloff; Emmanuell Diaz Carreño; Jimmy K. M. Valverde-Sánchez; Matthias Diener; Matheus da Silva Serpa; Guillaume Houzeaux; Lucas Mello Schnorr; Nicolas Maillard; Luciano Paschoal Gaspary; Philippe Olivier Alexandre Navaux (CARLA, 2016)

Automatic Communication Optimization of Parallel Applications in Public Clouds. - Emmanuell D. Carreño; Matthias Diener; Eduardo H. M. Cruz; Philippe O. A. Navaux (CCGrid, 2016)

Large vector extensions inside the HMC. - Marco A. Z. Alves; Matthias Diener; Paulo C. Santos 001; Luigi Carro (DATE, 2016)

A Sharing-Aware Memory Management Unit for Online Mapping in Multi-core Architectures. - Eduardo H. M. Cruz; Matthias Diener; Laércio Lima Pilla; Philippe O. A. Navaux (Euro-Par, 2016)

Communication in Shared Memory: Concepts, Definitions, and Efficient Detection. - Matthias Diener; Eduardo Henrique Molina da Cruz; Marco A. Z. Alves; Philippe O. A. Navaux (PDP, 2016)

Analyzing and Improving Memory Access Patterns of Large Irregular Applications on NUMA Machines. - Artur Mariano; Matthias Diener; Christian H. Bischof; Philippe O. A. Navaux (PDP, 2016)

Exploring Cache Size and Core Count Tradeoffs in Systems with Reduced Memory Access Latency. - Paulo C. Santos 001; Marco A. Z. Alves; Matthias Diener; Luigi Carro; Philippe O. A. Navaux (PDP, 2016)

LAPT: A locality-aware page table for thread and data mapping. - Eduardo Henrique Molina da Cruz; Matthias Diener; Marco A. Z. Alves; Laércio Lima Pilla; Philippe O. A. Navaux (Parallel Comput., 2016)

A dynamic block-level execution profiler. - Francis B. Moreira 001; Marco A. Z. Alves; Matthias Diener; Philippe O. A. Navaux; Israel Koren (Parallel Comput., 2016)

Hardware-Assisted Thread and Data Mapping in Hierarchical Multicore Architectures. - Eduardo H. M. Cruz; Matthias Diener; Laércio Lima Pilla; Philippe O. A. Navaux (ACM Trans. Archit. Code Optim., 2016)

Kernel-Based Thread and Data Mapping for Improved Memory Affinity. - Matthias Diener; Eduardo H. M. Cruz; Marco A. Z. Alves; Philippe O. A. Navaux; Anselm Busse; Hans-Ulrich Heiss (IEEE Trans. Parallel Distributed Syst., 2016)

Optimizing memory affinity with a hybrid compiler/OS approach. - Matthias Diener; Eduardo H. M. Cruz; Marco A. Z. Alves; Edson Borin; Philippe O. A. Navaux (Conf. Computing Frontiers, 2017)

Data mining the memory access stream to detect anomalous application behavior. - Francis B. Moreira 001; Matthias Diener; Philippe O. A. Navaux; Israel Koren (Conf. Computing Frontiers, 2017)

Leveraging Cloud Heterogeneity for Cost-Efficient Execution of Parallel Applications. - Eduardo Roloff; Matthias Diener; Emmanuell Diaz Carreño; Luciano Paschoal Gaspary; Philippe O. A. Navaux (Euro-Par, 2017)

HPC Application Performance and Cost Efficiency in the Cloud. - Eduardo Roloff; Matthias Diener; Luciano Paschoal Gaspary; Philippe O. A. Navaux (PDP, 2017)

Improving the memory access locality of hybrid MPI applications. - Matthias Diener; Sam White; Laxmikant V. Kalé; Michael T. Campbell; Daniel J. Bodony; Jonathan B. Freund (EuroMPI/USA, 2017)

Strategies to Improve the Performance of a Geophysics Model for Different Manycore Systems. - Matheus S. Serpa; Eduardo H. M. Cruz; Matthias Diener; Arthur M. Krause; Albert Farrés; Claudia Rosas; Jairo Panetta; Mauricio Hanzich; Philippe O. A. Navaux (SBAC-PAD (Workshops), 2017)

Integrating OpenMP into the Charm++ Programming Model. - Seonmyeong Bak; Harshitha Menon; Sam White; Matthias Diener; Laxmikant V. Kalé (ESPM2@SC, 2017)

Visualizing, Measuring, and Tuning Adaptive MPI Parameters. - Matthias Diener; Sam White; Laxmikant V. Kalé (ESPT/VPA@SC, 2017)

Exploiting Price and Performance Tradeoffs in Heterogeneous Clouds. - Eduardo Roloff; Matthias Diener; Emmanuell D. Carreño; Francis B. Moreira 001; Luciano Paschoal Gaspary; Philippe O. A. Navaux (UCC (Companion"), 2017)

Affinity-Based Thread and Data Mapping in Shared Memory Systems. - Matthias Diener; Eduardo H. M. Cruz; Marco A. Z. Alves; Philippe O. A. Navaux; Israel Koren (ACM Comput. Surv., 2017)

Modeling memory access behavior for data mapping. - Matthias Diener; Eduardo Henrique Molina da Cruz; Philippe Olivier Alexandre Navaux (Int. J. High Perform. Comput. Appl., 2017)

Multi-Level Load Balancing with an Integrated Runtime Approach. - Seonmyeong Bak; Harshitha Menon; Sam White; Matthias Diener; Laxmikant V. Kalé (CCGrid, 2018)

Exploiting Load Imbalance Patterns for Heterogeneous Cloud Computing Platforms. - Eduardo Roloff; Matthias Diener; Luciano Paschoal Gaspary; Philippe O. A. Navaux (CLOSER, 2018)

Improving Communication and Load Balancing with Thread Mapping in Manycore Systems. - Eduardo H. M. Cruz; Matthias Diener; Matheus S. Serpa; Philippe Olivier Alexandre Navaux; Laércio Lima Pilla; Israel Koren (PDP, 2018)

Accelerating Scientific Applications on Heterogeneous Systems with HybridOMP. - Matthias Diener; Daniel J. Bodony; Laxmikant V. Kalé (VECPAR, 2018)

Thread and Data Mapping for Multicore Systems - Improving Communication and Memory Accesses - Eduardo H. M. Cruz; Matthias Diener; Philippe O. A. Navaux (Springer, 2018)

Exploring Instance Heterogeneity in Public Cloud Providers for HPC Applications. - Eduardo Roloff; Matthias Diener; Luciano Paschoal Gaspary; Philippe O. A. Navaux (CLOSER, 2019)

Multi-phased Task Placement of HPC Applications in the Cloud. - Emmanuell D. Carreño; Marco A. Z. Alves; Matthias Diener; Eduardo Roloff; Philippe Olivier Alexandre Navaux (ISPDC, 2019)

Memory Performance and Bottlenecks in Multicore and GPU Architectures. - Matheus S. Serpa; Francis B. Moreira 001; Philippe O. A. Navaux; Eduardo H. M. Cruz; Matthias Diener; Dalvan Griebler; Luiz Gustavo Fernandes (PDP, 2019)

Managing Power Demand and Load Imbalance to Save Energy on Systems with Heterogeneous CPU Speeds. - Edson Luiz Padoin; Matthias Diener; Philippe O. A. Navaux; Jean-François Méhaut (SBAC-PAD, 2019)

Optimization strategies for geophysics models on manycore systems. - Matheus S. Serpa; Eduardo H. M. Cruz; Matthias Diener; Arthur M. Krause; Philippe O. A. Navaux; Jairo Panetta; Albert Farrés; Claudia Rosas; Mauricio Hanzich (Int. J. High Perform. Comput. Appl., 2019)

EagerMap: A Task Mapping Algorithm to Improve Communication and Load Balancing in Clusters of Multicore Systems. - Eduardo H. M. Cruz; Matthias Diener; Laércio Lima Pilla; Philippe O. A. Navaux (ACM Trans. Parallel Comput., 2019)

UIUC-PPL/charm: v6.10.0-beta1. - Laxmikant V. Kalé; Bilge Acun; Seonmyeong Bak; Aaron T. Becker; Milind A. Bhandarkar; Nitin Bhat; Abhinav Bhatele; Eric J. Bohm; Cyril Bordage; Robert Brunner; Ronak Buch; Sayantan Chakravorty; et al. (Zenodo, 2019)

UIUC-PPL/charm: v6.10.0-rc. - Laxmikant V. Kalé; Bilge Acun; Seonmyeong Bak; Aaron T. Becker; Milind A. Bhandarkar; Nitin Bhat; Abhinav Bhatele; Eric J. Bohm; Cyril Bordage; Robert Brunner; Ronak Buch; Sayantan Chakravorty; et al. (Zenodo, 2019)

UIUC-PPL/charm: v6.10.0-rc2. - Laxmikant V. Kalé; Bilge Acun; Seonmyeong Bak; Aaron T. Becker; Milind A. Bhandarkar; Nitin Bhat; Abhinav Bhatele; Eric J. Bohm; Cyril Bordage; Robert Brunner; Ronak Buch; Sayantan Chakravorty; et al. (Zenodo, 2019)

Characterizing the Sharing Behavior of Applications Using Software Transactional Memory. - Douglas Pereira Pasqualin; Matthias Diener; André Rauber Du Bois; Maurício Lima Pilla (Bench, 2020)

Unified data movement for offloading Charm++ applications. - Matthias Diener; Laxmikant V. Kalé (IPDPS Workshops, 2020)

Thread Affinity in Software Transactional Memory. - Douglas Pereira Pasqualin; Matthias Diener; André Rauber Du Bois; Maurício Lima Pilla (ISPDC, 2020)

Online Sharing-Aware Thread Mapping in Software Transactional Memory. - Douglas Pereira Pasqualin; Matthias Diener; André Rauber Du Bois; Maurício Lima Pilla (SBAC-PAD, 2020)

Heterogeneous computing with OpenMP and Hydra. - Matthias Diener; Laxmikant V. Kalé; Daniel J. Bodony (Concurr. Comput. Pract. Exp., 2020)

UIUC-PPL/charm: v6.10.0. - Laxmikant V. Kalé; Bilge Acun; Seonmyeong Bak; Aaron T. Becker; Milind A. Bhandarkar; Nitin Bhat; Abhinav Bhatele; Eric J. Bohm; Cyril Bordage; Robert Brunner; Ronak Buch; Sayantan Chakravorty; et al. (Zenodo, 2020)

UIUC-PPL/charm: v6.10.1. - Laxmikant V. Kalé; Bilge Acun; Seonmyeong Bak; Aaron T. Becker; Milind A. Bhandarkar; Nitin Bhat; Abhinav Bhatele; Eric J. Bohm; Cyril Bordage; Robert Brunner; Ronak Buch; Sayantan Chakravorty; et al. (Zenodo, 2020)

UIUC-PPL/charm: Charm++ version 6.10.2. - Laxmikant V. Kalé; Bilge Acun; Seonmyeong Bak; Aaron T. Becker; Milind A. Bhandarkar; Nitin Bhat; Abhinav Bhatele; Eric J. Bohm; Cyril Bordage; Robert Brunner; Ronak Buch; Sayantan Chakravorty; et al. (Zenodo, 2020)

UIUC-PPL/charm: v6.11.0-beta1. - Laxmikant V. Kalé; Bilge Acun; Seonmyeong Bak; Aaron T. Becker; Milind A. Bhandarkar; Nitin Bhat; Abhinav Bhatele; Eric J. Bohm; Cyril Bordage; Robert Brunner; Ronak Buch; Sayantan Chakravorty; et al. (Zenodo, 2020)

Current Requirements and Implementations in the field of Web Tracking in the pre-age of E-Privacy Regulation. - Christian Janßen; Matthias Diener; Jorge Marx Gómez (ECIS, 2021)

Performance Evaluation of Python Parallel Programming Models: and mpi4py. - Zane Fink; Simeng Liu; Jaemin Choi; Matthias Diener; Laxmikant V. Kalé (ESPM2@SC, 2021)

Sharing-Aware Data Mapping in Software Transactional Memory. - Douglas Pereira Pasqualin; Matthias Diener; André Rauber Du Bois; Maurício Lima Pilla (SAMOS, 2021)

Performance Evaluation of Python Parallel Programming Models: Charm4Py and mpi4py. - Zane Fink; Simeng Liu; Jaemin Choi; Matthias Diener; Laxmikant V. Kalé (CoRR, 2021)

Online Thread and Data Mapping Using a Sharing-Aware Memory Management Unit. - Eduardo H. M. Cruz; Matthias Diener; Laércio Lima Pilla; Philippe O. A. Navaux (ACM Trans. Model. Perform. Evaluation Comput. Syst., 2021)

UIUC-PPL/charm: v7.0.0-rc1. - Laxmikant V. Kalé; Bilge Acun; Seonmyeong Bak; Aaron T. Becker; Milind A. Bhandarkar; Nitin Bhat; Abhinav Bhatele; Eric J. Bohm; Cyril Bordage; Robert Brunner; Ronak Buch; Sayantan Chakravorty; et al. (Zenodo, 2021)

UIUC-PPL/charm: v7.0.0-rc2. - Laxmikant V. Kalé; Bilge Acun; Seonmyeong Bak; Aaron T. Becker; Milind A. Bhandarkar; Nitin Bhat; Abhinav Bhatele; Eric J. Bohm; Cyril Bordage; Robert Brunner; Ronak Buch; Sayantan Chakravorty; et al. (Zenodo, 2021)

UIUC-PPL/charm: Charm++ version 7.0.0. - Laxmikant V. Kalé; Bilge Acun; Seonmyeong Bak; Aaron T. Becker; Milind A. Bhandarkar; Nitin Bhat; Abhinav Bhatele; Eric J. Bohm; Cyril Bordage; Robert Brunner; Ronak Buch; Sayantan Chakravorty; et al. (Zenodo, 2021)

Mitigating execution unit contention in parallel applications using instruction-aware mapping. - Matheus S. Serpa; Eduardo H. M. Cruz; Matthias Diener; Arthur Francisco Lorenzon; Antonio C. S. Beck; Philippe O. A. Navaux (Concurr. Comput. Pract. Exp., 2023)

Thread and Data Mapping in Software Transactional Memory: an Overview. - Douglas Pereira Pasqualin; Matthias Diener; André Rauber Du Bois; Maurício Lima Pilla (Int. J. Parallel Program., 2025)