The Impact of Recent DRAM Architectures on Embedded Systems Performance. - Matthias Gries (EUROMICRO, 2000)

Embedded Software in Network Processors - Models and Algorithms. - Lothar Thiele; Samarjit Chakraborty; Matthias Gries; Alexander Maxiaguine; Jonas Greutert (EMSOFT, 2001)

FunState-an internal design representation for codesign. - Karsten Strehl; Lothar Thiele; Matthias Gries; Dirk Ziegenbein; Rolf Ernst; Jürgen Teich (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Algorithm architecture trade offs in network processor design. - Matthias Gries (Shaker, 2001)

A framework for evaluating design tradeoffs in packet processing architectures. - Lothar Thiele; Samarjit Chakraborty; Matthias Gries; Simon Künzli 001 (DAC, 2002)

Supporting a Low Delay Best-Effort Class in the Presence of Real-Time Traffic. - Samarjit Chakraborty; Matthias Gries; Lothar Thiele (IEEE Real Time Technology and Applications Symposium, 2002)

Programming challenges in network processor deployment. - Chidamber Kulkarni; Matthias Gries; Christian Sauer 001; Kurt Keutzer (CASES, 2003)

Comparing Analytical Modeling with Simulation for Network Processors: A Case Study. - Matthias Gries; Chidamber Kulkarni; Christian Sauer 001; Kurt Keutzer (DATE, 2003)

Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures. - Scott J. Weber; Matthew W. Moskewicz; Matthias Gries; Christian Sauer 001; Kurt Keutzer (CODES+ISSS, 2004)

Developing a Flexible Interface for RapidIO, Hypertransport, and PCI-Express. - Christian Sauer 001; Matthias Gries; José Ignacio Gómez; Scott J. Weber; Kurt Keutzer (PARELEC, 2004)

Methods for evaluating and covering the design space during early design development. - Matthias Gries (Integr., 2004)

Modular domain-specific implementation and exploration framework for embedded software platforms. - Christian Sauer 001; Matthias Gries; Sören Sonntag (DAC, 2005)

Application-Driven Design of Cost-Efficient Communications Platforms. - Hans-Martin Blüthgen; Christian Sauer 001; Dominik Langen; Matthias Gries; Wolfgang Raab (GI Jahrestagung (1), 2005)

Performance Evaluation of VLSI platforms using SystemQ. - Sören Sonntag; Matthias Gries; Christian Sauer 001 (GI Jahrestagung (1), 2005)

Modular Reference Implementation of an IP-DSLAM. - Christian Sauer 001; Matthias Gries; Sören Sonntag (ISCC, 2005)

Trends in Access Networks and their Implementation in DSLAMs. - Christian Sauer 001; Matthias Gries; Sören Sonntag; Dietmar Toelle; Bo Wu; Rudi Knorr (LCN, 2005)

SystemQ: A Queuing-Based Approach to Architecture Performance Evaluation with SystemC. - Sören Sonntag; Matthias Gries; Christian Sauer 001 (SAMOS, 2005)

Performance Evaluation of Packet Processing Architectures Using Multiclass Queuing Networks. - Sören Sonntag; Matthias Gries; Christian Sauer 001 (Annual Simulation Symposium, 2006)

Application-Driven Development of Concurrent Packet Processing Platforms. - Christian Sauer 001; Matthias Gries; Jörg-Christian Niemann; Mario Porrmann; Michael Thies (PARELEC, 2006)

Interactive presentation: Hard- and software modularity of the NOVA MPSoC platform. - Christian Sauer 001; Matthias Gries; Sebastian Dirk (DATE, 2007)

SystemQ: Bridging the gap between queuing-based performance evaluation and SystemC. - Sören Sonntag; Matthias Gries; Christian Sauer 001 (Des. Autom. Embed. Syst., 2007)

SystemClick: a domain-specific framework for early exploration using functional performance models. - Christian Sauer 001; Matthias Gries; Hans-Peter Löb (DAC, 2008)

Implementing a Software-Based 802.11 MAC on a Customized Platform. - Hans-Peter Loeb; Matthias Gries; Christian Sauer 001 (CCNC, 2009)

A virtual platform environment for exploring power, thermal and reliability management control strategies in high-performance multicores. - Andrea Bartolini; Matteo Cacciari; Andrea Tilli; Luca Benini; Matthias Gries (ACM Great Lakes Symposium on VLSI, 2010)

LMS-based low-complexity game workload prediction for DVFS. - Benedikt Dietrich; Swaroop Nunna; Dip Goswami; Samarjit Chakraborty; Matthias Gries (ICCD, 2010)

A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS. - Jason Howard; Saurabh Dighe; Yatin Vasant Hoskote; Sriram R. Vangal; David Finan; Gregory Ruhl; David Jenkins; Howard Wilson; Nitin Borkar; Gerhard Schrom; Fabric Pailet; Shailendra Jain; et al. (ISSCC, 2010)

Phase-Based Application-Driven Hierarchical Power Management on the Single-chip Cloud Computer. - Nikolas Ioannou; Michael Kauschke; Matthias Gries; Marcelo Cintra (PACT, 2011)

SCC: A Flexible Architecture for Many-Core Platform Research. - Matthias Gries; Ulrich Hoffmann; Michael Konow; Michael Riepen (Comput. Sci. Eng., 2011)

A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling. - Jason Howard; Saurabh Dighe; Sriram R. Vangal; Gregory Ruhl; Nitin Borkar; Shailendra Jain; Vasantha Erraguntla; Michael Konow; Michael Riepen; Matthias Gries; Guido Droege; Tor Lund-Larsen; et al. (IEEE J. Solid State Circuits, 2011)

Time Series Characterization of Gaming Workload for Runtime Power Management. - Benedikt Dietrich; Dip Goswami; Samarjit Chakraborty; Apratim Guha; Matthias Gries (IEEE Trans. Computers, 2015)