Energy Efficient Acceleration and Evaluation of Financial Computations towards Real-Time Pricing. - Christian de Schryver; Matthias Jung 001; Norbert Wehn; Henning Marxen; Anton Kostiuk; Ralf Korn (KES (4), 2011)

TLM modelling of 3D stacked wide I/O DRAM subsystems: a virtual platform for memory controller design space exploration. - Matthias Jung 001; Christian Weis; Norbert Wehn; Karthik Chandrasekar 001 (RAPIDO, 2013)

Energy optimization in 3D MPSoCs with Wide-I/O DRAM using temperature variation aware bank-wise refresh. - MohammadSadegh Sadri; Matthias Jung 001; Christian Weis; Norbert Wehn; Luca Benini (DATE, 2014)

Optimized active and power-down mode refresh control in 3D-DRAMs. - Matthias Jung 001; Christian Weis; Norbert Wehn; MohammadSadegh Sadri; Luca Benini (VLSI-SoC, 2014)

Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs. - Christian Weis; Matthias Jung 001; Peter Ehses; Cristiano Santos; Pascal Vivet; Sven Goossens; Martijn Koedam; Norbert Wehn (DATE, 2015)

A Custom Computing System for Finding Similarties in Complex Networks. - Christian Brugger; Valentin Grigorovici; Matthias Jung 001; Christian Weis; Christian de Schryver; Katharina Anna Zweig; Norbert Wehn (ISVLSI, 2015)

Thermal Aspects and High-Level Explorations of 3D Stacked DRAMs. - Christian Weis; Matthias Jung 001; Omar Naji; Norbert Wehn; Cristiano Santos; Pascal Vivet; Andreas Hansson 001 (ISVLSI, 2015)

Omitting Refresh: A Case Study for Commodity and Wide I/O DRAMs. - Matthias Jung 001; Éder Zulian; Deepak M. Mathew; Matthias Herrmann; Christian Brugger; Christian Weis; Norbert Wehn (MEMSYS, 2015)

A high-level DRAM timing, power and area exploration tool. - Omar Naji; Christian Weis; Matthias Jung 001; Norbert Wehn; Andreas Hansson 001 (SAMOS, 2015)

DRAMSys: A Flexible DRAM Subsystem Design Space Exploration Framework. - Matthias Jung 001; Christian Weis; Norbert Wehn (IPSJ Trans. Syst. LSI Des. Methodol., 2015)

Efficient reliability management in SoCs - an approximate DRAM perspective. - Matthias Jung 001; Deepak M. Mathew; Christian Weis; Norbert Wehn (ASP-DAC, 2016)

Invited - Approximate computing with partially unreliable dynamic random access memory - approximate DRAM. - Matthias Jung 001; Deepak M. Mathew; Christian Weis; Norbert Wehn (DAC, 2016)

ConGen: An Application Specific DRAM Memory Controller Generator. - Matthias Jung 001; Deepak M. Mathew; Christian Weis; Norbert Wehn; Irene Heinrich; Marco V. Natale; Sven O. Krumke (MEMSYS, 2016)

Reverse Engineering of DRAMs: Row Hammer with Crosshair. - Matthias Jung 001; Carl Christian Rheinländer; Christian Weis; Norbert Wehn (MEMSYS, 2016)

A new bank sensitive DRAMPower model for efficient design space exploration. - Matthias Jung 001; Deepak M. Mathew; Éder F. Zulian; Christian Weis; Norbert Wehn (PATMOS, 2016)

Exploring system performance using elastic traces: Fast, accurate and portable. - Radhika Jagtap; Stephan Diestelhorst; Andreas Hansson 001; Matthias Jung 001; Norbert Wehn (SAMOS, 2016)

A cross layer approach for efficient thermal management in 3D stacked SoCs. - Matthias Jung 001; Christian Weis; Norbert Wehn (Microelectron. Reliab., 2016)

Integrating DRAM power-down modes in gem5 and quantifying their impact. - Radhika Jagtap; Matthias Jung 001; Wendy Elsasser; Christian Weis; Andreas Hansson 001; Norbert Wehn (MEMSYS, 2017)

Using run-time reverse-engineering to optimize DRAM refresh. - Deepak M. Mathew; Éder F. Zulian; Matthias Jung 001; Kira Kraft; Christian Weis; Bruce L. Jacob; Norbert Wehn (MEMSYS, 2017)

A Bank-Wise DRAM Power Model for System Simulations. - Deepak M. Mathew; Éder F. Zulian; Subash Kannoth; Matthias Jung 001; Christian Weis; Norbert Wehn (RAPIDO, 2017)

A new state model for DRAMs using Petri Nets. - Matthias Jung 001; Kira Kraft; Norbert Wehn (SAMOS, 2017)

Supervised testing of concurrent software in embedded systems. - Jasmin Jahic; Thomas Kuhn 001; Matthias Jung 001; Norbert Wehn (SAMOS, 2017)

System simulation with gem5 and SystemC: The keystone for full interoperability. - Christian Menard; Jerónimo Castrillón; Matthias Jung 001; Norbert Wehn (SAMOS, 2017)

A Platform to Analyze DDR3 DRAM's Power and Retention Time. - Matthias Jung 001; Deepak M. Mathew; Carl Christian Rheinländer; Christian Weis; Norbert Wehn (IEEE Des. Test, 2017)

3D-Stacked Many-Core Architecture for Biological Sequence Analysis Problems. - Pei Liu 003; Ahmed Hemani; Kolin Paul; Christian Weis; Matthias Jung 001; Norbert Wehn (Int. J. Parallel Program., 2017)

DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool. - Christian Weis; Abdul Mutaal; Omar Naji; Matthias Jung 001; Andreas Hansson 001; Norbert Wehn (Int. J. Parallel Program., 2017)

A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D-Stacked Architecture. - Pei Liu 003; Ahmed Hemani; Kolin Paul; Christian Weis; Matthias Jung 001; Norbert Wehn (J. Signal Process. Syst., 2017)

Improving the error behavior of DRAM by exploiting its Z-channel property. - Kira Kraft; Chirag Sudarshan; Deepak M. Mathew; Christian Weis; Norbert Wehn; Matthias Jung 001 (DATE, 2018)

An analysis on retention error behavior and power consumption of recent DDR4 DRAMs. - Deepak M. Mathew; Martin Schultheis; Carl Christian Rheinländer; Chirag Sudarshan; Christian Weis; Norbert Wehn; Matthias Jung 001 (DATE, 2018)

Enabling Continuous Software Engineering for Embedded Systems Architectures with Virtual Prototypes. - Pablo Oliveira Antonino; Matthias Jung 001; Andreas Morgenstern; Florian Faßnacht; Thomas Bauer 002; Adam Bachorek; Thomas Kuhn 001; Elisa Yumi Nakagawa (ECSA, 2018)

The Role of Memories in Transprecision Computing. - Christian Weis; Matthias Jung 001; Éder F. Zulian; Chirag Sudarshan; Deepak M. Mathew; Norbert Wehn (ISCAS, 2018)

Driving into the memory wall: the role of memory for advanced driver assistance systems and autonomous driving. - Matthias Jung 001; Sally A. McKee; Chirag Sudarshan; Christoph Dropmann; Christian Weis; Norbert Wehn (MEMSYS, 2018)

Efficient coding scheme for DDR4 memory subsystems. - Kira Kraft; Deepak M. Mathew; Chirag Sudarshan; Matthias Jung 001; Christian Weis; Norbert Wehn; Florian Longnos (MEMSYS, 2018)

A Framework for Non-intrusive Trace-driven Simulation of Manycore Architectures with Dynamic Tracing Configuration. - Jasmin Jahic; Matthias Jung 001; Thomas Kuhn 001; Claus Kestel; Norbert Wehn (RV, 2018)

A Model-Based Safety Analysis of Dependencies Across Abstraction Layers. - Christoph Dropmann; Eike Thaden; Mario Trapp; Denis Uecker; Rakshith Amarnath; Leandro Avila da Silva; Peter Munk; Markus Schweizer; Matthias Jung 001; Rasmus Adler (SAFECOMP, 2018)

BOSMI: a framework for non-intrusive monitoring and testing of embedded multithreaded software on the logical level. - Jasmin Jahic; Thomas Kuhn 001; Matthias Jung 001; Norbert Wehn (SAMOS, 2018)

A Memory Centric Architecture of the Link Assessment Algorithm in Large Graphs. - Christian Brugger; Valentin Grigorovici; Matthias Jung 001; Christian de Schryver; Christian Weis; Norbert Wehn; Katharina Anna Zweig (IEEE Des. Test, 2018)

Speculative Temporal Decoupling Using fork(). - Matthias Jung 001; Frank Schnicke; Markus Damm; Thomas Kuhn 001; Norbert Wehn (DATE, 2019)

Rapid Identification of Shared Memory in Multithreaded Embedded Systems with Static Scheduling. - Jasmin Jahic; Varun Kumar; Matthias Jung 001; Gerhard Wirrer; Norbert Wehn; Thomas Kuhn 001 (ICPP Workshops, 2019)

An In-DRAM Neural Network Processing Engine. - Chirag Sudarshan; Jan Lappas; Muhammad Mohsin Ghaffar; Vladimir Rybalkin; Christian Weis; Matthias Jung 001; Norbert Wehn (ISCAS, 2019)

Fast validation of DRAM protocols with timed petri nets. - Matthias Jung 001; Kira Kraft; Taha Soliman; Chirag Sudarshan; Christian Weis; Norbert Wehn (MEMSYS, 2019)

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM. - Deepak M. Mathew; André Lucas Chinazzo; Christian Weis; Matthias Jung 001; Bastien Giraud; Pascal Vivet; Alexandre Levisse; Norbert Wehn (SAMOS, 2019)

A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing. - Chirag Sudarshan; Jan Lappas; Christian Weis; Deepak M. Mathew; Matthias Jung 001; Norbert Wehn (SAMOS, 2019)

eBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex. - Dimitrios Stathis 001; Chirag Sudarshan; Yu Yang; Matthias Jung 001; Syed Mohammad Asad Hassan Jafri; Christian Weis; Ahmed Hemani; Anders Lansner; Norbert Wehn (CoRR, 2019)

Fast and Accurate DRAM Simulation: Can we Further Accelerate it? - Johannes Feldmann; Kira Kraft; Lukas Steiner; Norbert Wehn; Matthias Jung 001 (DATE, 2020)

A Low Power In-DRAM Architecture for Quantized CNNs using Fast Winograd Convolutions. - Muhammad Mohsin Ghaffar; Chirag Sudarshan; Christian Weis; Matthias Jung 001; Norbert Wehn (MEMSYS, 2020)

An Energy Efficient 3D-Heterogeneous Main Memory Architecture for Mobile Devices. - Deepak M. Mathew; Felipe S. Prado; Éder F. Zulian; Christian Weis; Muhammad Mohsin Ghaffar; Matthias Jung 001; Norbert Wehn (MEMSYS, 2020)

Efficient Generation of Application Specific Memory Controllers. - Marco V. Natale; Matthias Jung 001; Kira Kraft; Frederik Lauer; Johannes Feldmann; Chirag Sudarshan; Christian Weis; Sven Oliver Krumke; Norbert Wehn (MEMSYS, 2020)

System simulation with PULP virtual platform and SystemC. - Éder F. Zulian; Germain Haugou; Christian Weis; Matthias Jung 001; Norbert Wehn (RAPIDO, 2020)

DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator. - Lukas Steiner; Matthias Jung 001; Felipe S. Prado; Kirill Bykov; Norbert Wehn (SAMOS, 2020)

The gem5 Simulator: Version 20.0+. - Jason Lowe-Power; Abdul Mutaal Ahmad; Ayaz Akram; Mohammad Alian; Rico Amslinger; Matteo Andreozzi; Adrià Armejach; Nils Asmussen; Srikant Bharadwaj; Gabe Black; Gedare Bloom; Bobby R. Bruce; et al. (CoRR, 2020)

eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex. - Dimitrios Stathis 001; Chirag Sudarshan; Yu Yang; Matthias Jung 001; Christian Weis; Ahmed Hemani; Anders Lansner; Norbert Wehn (J. Signal Process. Syst., 2020)

A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs. - Chirag Sudarshan; Taha Soliman; Cecilia De la Parra; Christian Weis; Leonardo Ecco; Matthias Jung 001; Norbert Wehn; Andre Guntoro (ASP-DAC, 2021)

The Dynamic Random Access Memory Challenge in Embedded Computing Systems. - Matthias Jung 001; Christian Weis; Norbert Wehn (A Journey of Embedded and Cyber-Physical Systems, 2021)

Exploration of DDR5 with the Open-Source Simulator DRAMSys. - Lukas Steiner; Matthias Jung 001; Norbert Wehn (MBMV, 2021)

An LPDDR4 Safety Model for Automotive Applications. - Lukas Steiner; Kira Kraft; Denis Uecker; Matthias Jung 001; Michael Huonker; Norbert Wehn (MEMSYS, 2021)

Online Working Set Change Detection with Constant Complexity: The Cornerstone for Memory Management Algorithms in Scalable Systems. - L. J. Gokul Vasan; Éder F. Zulian; Christian Weis; Matthias Jung 001; Norbert Wehn (MEMSYS, 2021)

SEC-Learn: Sensor Edge Cloud for Federated Learning - Invited Paper. - Patrick Aichroth; Christoph Antes; Pierre Gembatzka; Holger Graf; David S. Johnson 003; Matthias Jung 001; Thomas Kämpfe; Thomas Kleinberger; Thomas Köllmer; Thomas Kuhn 001; Christoph Kutter; Jens Krüger 004; et al. (SAMOS, 2021)

A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation. - Chirag Sudarshan; Lukas Steiner; Matthias Jung 001; Jan Lappas; Christian Weis; Norbert Wehn (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Unveiling the Real Performance of LPDDR5 Memories. - Lukas Steiner; Matthias Jung 001; Michael Huonker; Norbert Wehn (MEMSYS, 2022)

A Framework for Formal Verification of DRAM Controllers. - Lukas Steiner; Chirag Sudarshan; Matthias Jung 001; Dominik Stoffel; Norbert Wehn (MEMSYS, 2022)

Split'n'Cover: ISO 26262 Hardware Safety Analysis with SystemC. - Denis Uecker; Matthias Jung 001 (SAMOS, 2022)

A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference. - Chirag Sudarshan; Taha Soliman; Jan Lappas; Christian Weis; Mohammad Hassani Sadi; Matthias Jung 001; Andre Guntoro; Norbert Wehn (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

Guest Editorial: Special Issue on 2020 IEEE International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2020). - Marc Reichenbach; Matthias Jung 001; Alex Orailoglu (Int. J. Parallel Program., 2022)

DRAMSys4.0: An Open-Source Simulation Framework for In-depth DRAM Analyses. - Lukas Steiner; Matthias Jung 001; Felipe S. Prado; Kirill Bykov; Norbert Wehn (Int. J. Parallel Program., 2022)

Automatic DRAM Subsystem Configuration with irace. - Lukas Steiner; Gustavo Delazeri; Iron Prando da Silva; Matthias Jung 001; Norbert Wehn (DroneSE/RAPIDO@HiPEAC, 2023)

A Precise Measurement Platform for LPDDR4 Memories. - Johannes Feldmann; Lukas Steiner; Derek Christ; Thomas Psota; Matthias Jung 001; Norbert Wehn (MEMSYS, 2023)

Challenges for Quantum Software Engineering: An Industrial Application Scenario Perspective. - Cecilia Carbonelli; Michael Felderer; Matthias Jung 001; Elisabeth Lobe; Malte Lochau; Sebastian Luber; Wolfgang Mauerer; Rudolf Ramler; Ina Schaefer; Christoph Schroth (Quantum Software, 2024)

The New Costs of Physical Memory Fragmentation. - Alexander Halbuer; Illia Ostapyshyn; Lukas Steiner; Lars Wrenger; Matthias Jung 001; Christian Dietrich 001; Daniel Lohmann (DIMES@SOSP, 2024)

PIMSys: A Virtual Prototype for Processing in Memory. - Derek Christ; Lukas Steiner; Matthias Jung 001; Norbert Wehn (MEMSYS, 2024)

A Novel System Simulation Framework for HBM2 FPGA Platforms. - Hector Gerardo Muñoz Hernandez; Veronia Iskandar; Lukas Steiner; Philipp Holzinger; Matthias Jung 001; Diana Göhringer; Michael Hübner 001; Norbert Wehn; Marc Reichenbach (SAMOS, 2024)

QCEDA: Using Quantum Computers for EDA. - Matthias Jung 001; Sven O. Krumke; Christof Schroth; Elisabeth Lobe; Wolfgang Mauerer (SAMOS, 2024)

Special Issue on SAMOS 2022. - Alex Orailoglu; Marc Reichenbach; Matthias Jung 001 (Int. J. Parallel Program., 2024)

Architecture, Simulation and Software Stack to Support Post-CMOS Accelerators: The ARCHYTAS Project. - Giovanni Agosta; Stefano Cherubin; Derek Christ; Francesco Conti 001; Asbjørn Djupdal; Matthias Jung 001; Georgios Keramidas; Roberto Passerone; Paolo Rech; Elisa Ricci 001; Philippe Velha; Flavio Vella; et al. (ISVLSI, 2025)

DRAMPower 5: An Open-Source Power Simulator for Current Generation DRAM Standards. - Lukas Steiner; Thomas Psota; Marco Mörz; Derek Christ; Matthias Jung 001; Norbert Wehn (RAPIDO@HiPEAC, 2025)

Split'n'Cover: ISO 26262 Hardware Safety Analysis with SystemC. - Lukas Steiner; Kira Kraft; Derek Christ; Denis Uecker; Christian Malek; Matthias Jung 001; Norbert Wehn (Int. J. Parallel Program., 2025)

Correction: Split'n'Cover: ISO 26,262 Hardware Safety Analysis with SystemC. - Lukas Steiner; Kira Kraft; Derek Christ; Denis Uecker; Christian Malek; Matthias Jung 001; Norbert Wehn (Int. J. Parallel Program., 2025)