Low power register file architecture for application specific DSPs. - Matthias Müller 002; Andreas Wortmann 002; Sven Simon 001; S. Wolter; Steffen Buch; Marek Wróblewski; Josef A. Nossek (ISCAS (4), 2002)

A power efficient register file architecture using master latch sharing. - Marek Wróblewski; Matthias Müller 002; Andreas Wortmann 002; Sven Simon 001; Wilhelm Pieper; Josef A. Nossek (ISCAS (5), 2003)

A High-Speed Transceiver Architecture Implementable as Synthesizable IP Core. - Andreas Wortmann 002; Sven Simon 001; Matthias Müller 002 (DATE, 2004)

The impact of clock gating schemes on the power dissipation of synthesizable register files. - Matthias Müller 002; Andreas Wortmann 002; Sven Simon 001; Michael Kugel; Tim Schoenauer (ISCAS (2), 2004)

An instruction set for the efficient implementation of the CORDIC algorithm. - Sven Simon 001; Matthias Müller 002; Holger Gryska; Andreas Wortmann 002; Steffen Buch (ISCAS (2), 2004)

Register Isolation for Synthesizable Register Files. - Matthias Müller 002; Andreas Wortmann 002; Dominik Mader; Sven Simon 001 (PATMOS, 2004)

A power dissipation comparison of ALU-architectures for ASIPs. - Vijayakumar Kalyanaraman; Matthias Müller 002; Sven Simon 001; Mario Steinert; Holger Gryska (ECCTD, 2005)

Power reduction of ASIPs by distributing the workload on several ASIP-instances. - Vijayakumar Kalyanaraman; Matthias Müller 002; Sven Simon 001; Mario Steinert; Holger Gryska (ECCTD, 2005)

Datenskalierung für die verlustleistungsarme Signalverarbeitung in Prozessorsystemen. - Matthias Müller 002; Sven Simon 001 (GI Jahrestagung (1), 2005)

Low power synthesizable register files for processor and IP cores. - Matthias Müller 002; Sven Simon 001; Holger Gryska; Andreas Wortmann 002; Steffen Buch (Integr., 2006)