Efficient SAT-Based Search for Longest Sensitisable Paths. - Matthias Sauer 002; Jie Jiang 018; Alejandro Czutro; Ilia Polian; Bernd Becker 001 (Asian Test Symposium, 2011)

SAT-based analysis of sensitisable paths. - Matthias Sauer 002; Alexander Czutro; Tobias Schubert 001; Stefan Hillebrecht; Ilia Polian; Bernd Becker 001 (DDECS, 2011)

Estimation of component criticality in early design steps. - Matthias Sauer 002; Alejandro Czutro; Ilia Polian; Bernd Becker 001 (IOLTS, 2011)

An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors. - Matthias Sauer 002; Victor Tomashevich; Jörg Müller 004; Matthew Lewis 004; Andreas Spilla; Ilia Polian; Bernd Becker 001; Wolfram Burgard (IOLTS, 2011)

Variation-Aware Fault Grading. - Alexander Czutro; Michael E. Imhof; J. Jiang; Abdullah Mumtaz; Matthias Sauer 002; Bernd Becker 001; Ilia Polian; Hans-Joachim Wunderlich (Asian Test Symposium, 2012)

On the optimality of K longest path generation algorithm under memory constraints. - Jie Jiang 018; Matthias Sauer 002; Alexander Czutro; Bernd Becker 001; Ilia Polian (DATE, 2012)

#SAT-based vulnerability analysis of security components - A case study. - Linus Feiten; Matthias Sauer 002; Tobias Schubert 001; Alexander Czutro; Eberhard Böhl; Ilia Polian; Bernd Becker 001 (DFT, 2012)

Multi-conditional SAT-ATPG for power-droop testing. - Alexander Czutro; Matthias Sauer 002; Ilia Polian; Bernd Becker 001 (ETS, 2012)

On the quality of test vectors for post-silicon characterization. - Matthias Sauer 002; Alexander Czutro; Bernd Becker 001; Ilia Polian (ETS, 2012)

Small-delay-fault ATPG with waveform accuracy. - Matthias Sauer 002; Alexander Czutro; Ilia Polian; Bernd Becker 001 (ICCAD, 2012)

Functional test of small-delay faults using SAT and Craig interpolation. - Matthias Sauer 002; Stefan Kupferschmid; Alexander Czutro; Ilia Polian; Sudhakar M. Reddy; Bernd Becker 001 (ITC, 2012)

Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation. - Matthias Sauer 002; Stefan Kupferschmid; Alejandro Czutro; Sudhakar M. Reddy; Bernd Becker 001 (VLSI Design, 2012)

SAT-ATPG using preferences for improved detection of complex defect mechanisms. - Alexander Czutro; Matthias Sauer 002; Tobias Schubert 001; Ilia Polian; Bernd Becker 001 (VTS, 2012)

Provably optimal test cube generation using quantified boolean formula solving. - Matthias Sauer 002; Sven Reimer; Ilia Polian; Tobias Schubert 001; Bernd Becker 001 (ASP-DAC, 2013)

Accurate Multi-cycle ATPG in Presence of X-Values. - Dominik Erb; Michael A. Kochte; Matthias Sauer 002; Hans-Joachim Wunderlich; Bernd Becker 001 (Asian Test Symposium, 2013)

Search Space Reduction for Low-Power Test Generation. - Kohei Miyase; Matthias Sauer 002; Bernd Becker 001; Xiaoqing Wen; Seiji Kajihara (Asian Test Symposium, 2013)

Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics. - Young Moon Kim; Jun Seomun; Hyung-Ock Kim; Kyung Tae Do; Jung Yun Choi; Kee Sup Kim; Matthias Sauer 002; Bernd Becker 001; Subhasish Mitra (CICC, 2013)

Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths. - Matthias Sauer 002; Sven Reimer; Tobias Schubert 001; Ilia Polian; Bernd Becker 001 (DATE, 2013)

Equivalence checking of partial designs using dependency quantified Boolean formulae. - Karina Gitina; Sven Reimer; Matthias Sauer 002; Ralf Wimmer 001; Christoph Scholl 001; Bernd Becker 001 (ICCD, 2013)

Early-life-failure detection using SAT-based ATPG. - Matthias Sauer 002; Young Moon Kim; Jun Seomun; Hyung-Ock Kim; Kyung Tae Do; Jung Yun Choi; Kee Sup Kim; Subhasish Mitra; Bernd Becker 001 (ITC, 2013)

Accurate Computation of Sensitizable Paths Using Answer Set Programming. - Benjamin Andres; Matthias Sauer 002; Martin Gebser; Tobias Schubert 001; Bernd Becker 001; Torsten Schaub (LPNMR, 2013)

Equivalence Checking for Partial Implementations Revisited. - Karina Gitina; Sven Reimer; Matthias Sauer 002; Ralf Wimmer 001; Christoph Scholl 001; Bernd Becker 001 (MBMV, 2013)

Identification of critical variables using an FPGA-based fault injection framework. - Andreas Riefert; Jörg Müller 004; Matthias Sauer 002; Wolfram Burgard; Bernd Becker 001 (VTS, 2013)

SAT-Based Analysis of Sensitizable Paths. - Matthias Sauer 002; Alexander Czutro; Tobias Schubert 001; Stefan Hillebrecht; Ilia Polian; Bernd Becker 001 (IEEE Des. Test, 2013)

Implementation and Analysis of Ring Oscillator PUFs on 60 nm Altera Cyclone FPGAs. - Linus Feiten; Andreas Spilla; Matthias Sauer 002; Tobias Schubert 001; Bernd Becker 001 (Inf. Secur. J. A Glob. Perspect., 2013)

Circuit Parameter Independent Test Pattern Generation for Interconnect Open Defects. - Dominik Erb; Karsten Scheibler; Matthias Sauer 002; Sudhakar M. Reddy; Bernd Becker 001 (ATS, 2014)

Incremental Encoding and Solving of Cardinality Constraints. - Sven Reimer; Matthias Sauer 002; Tobias Schubert 001; Bernd Becker 001 (ATVA, 2014)

A Formal Approach to the Traveling Professor Problem. - Matthias Sauer 002; Stefan Kupferschmid (Aspekte der Technischen Informatik, 2014)

Efficient SMT-based ATPG for interconnect open defects. - Dominik Erb; Karsten Scheibler; Matthias Sauer 002; Bernd Becker 001 (DATE, 2014)

Using MaxBMC for Pareto-optimal circuit initialization. - Sven Reimer; Matthias Sauer 002; Tobias Schubert 001; Bernd Becker 001 (DATE, 2014)

An effective approach to automatic functional processor test generation for small-delay faults. - Andreas Riefert; Lyl M. Ciganda; Matthias Sauer 002; Paolo Bernardi; Matteo Sonza Reorda; Bernd Becker 001 (DATE, 2014)

Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization. - Bernd Becker 001; Rolf Drechsler; Stephan Eggersglüß; Matthias Sauer 002 (DTIS, 2014)

Variation-aware deterministic ATPG. - Matthias Sauer 002; Ilia Polian; Michael E. Imhof; Abdullah Mumtaz; Eric Schneider; Alexander Czutro; Hans-Joachim Wunderlich; Bernd Becker 001 (ETS, 2014)

Test pattern generation in presence of unknown values based on restricted symbolic logic. - Dominik Erb; Karsten Scheibler; Michael A. Kochte; Matthias Sauer 002; Hans-Joachim Wunderlich; Bernd Becker 001 (ITC, 2014)

Efficient SAT-Based Circuit Initialization for Larger Designs. - Matthias Sauer 002; Sven Reimer; Sudhakar M. Reddy; Bernd Becker 001 (VLSID, 2014)

QBF with Soft Variables. - Sven Reimer; Matthias Sauer 002; Paolo Marin; Bernd Becker 001 (Electron. Commun. Eur. Assoc. Softw. Sci. Technol., 2014)

Exact Logic and Fault Simulation in Presence of Unknowns. - Dominik Erb; Michael A. Kochte; Matthias Sauer 002; Stefan Hillebrecht; Tobias Schubert 001; Hans-Joachim Wunderlich; Bernd Becker 001 (ACM Trans. Design Autom. Electr. Syst., 2014)

Testing time - time to test?: using formal methods for the timing analysis of digital circuits. - Matthias Sauer 002 (Der Andere Verlag, 2014)

Solving DQBF through quantifier elimination. - Karina Gitina; Ralf Wimmer 001; Sven Reimer; Matthias Sauer 002; Christoph Scholl 001; Bernd Becker 001 (DATE, 2015)

On the automatic generation of SBST test programs for in-field test. - Andreas Riefert; Riccardo Cantoro; Matthias Sauer 002; Matteo Sonza Reorda; Bernd Becker 001 (DATE, 2015)

Improving RO-PUF quality on FPGAs by incorporating design-dependent frequency biases. - Linus Feiten; Tobias Martin; Matthias Sauer 002; Bernd Becker 001 (ETS, 2015)

Identification of high power consuming areas with gate type and logic level information. - Kohei Miyase; Matthias Sauer 002; Bernd Becker 001; Xiaoqing Wen; Seiji Kajihara (ETS, 2015)

Modeling Unknown Values in Test and Verification. - Bernd Becker 001; Matthias Sauer 002; Christoph Scholl 001; Ralf Wimmer 001 (SyDe Summer School, 2015)

Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects. - Dominik Erb; Karsten Scheibler; Matthias Sauer 002; Sudhakar M. Reddy; Bernd Becker 001 (VTS, 2015)

Improving diagnosis resolution of a fault detection test set. - Andreas Riefert; Matthias Sauer 002; Sudhakar M. Reddy; Bernd Becker 001 (VTS, 2015)

Accurate QBF-Based Test Pattern Generation in Presence of Unknown Values. - Dominik Erb; Michael A. Kochte; Sven Reimer; Matthias Sauer 002; Hans-Joachim Wunderlich; Bernd Becker 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Formal Vulnerability Analysis of Security Components. - Linus Feiten; Matthias Sauer 002; Tobias Schubert 001; Victor Tomashevich; Ilia Polian; Bernd Becker 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Mixed 01X-RSL-Encoding for fast and accurate ATPG with unknowns. - Dominik Erb; Karsten Scheibler; Michael A. Kochte; Matthias Sauer 002; Hans-Joachim Wunderlich; Bernd Becker 001 (ASP-DAC, 2016)

On Optimal Power-Aware Path Sensitization. - Matthias Sauer 002; Jie Jiang 018; Sven Reimer; Kohei Miyase; Xiaoqing Wen; Bernd Becker 001; Ilia Polian (ATS, 2016)

Formal verification of secure reconfigurable scan network infrastructure. - Michael A. Kochte; Rafal Baranowski; Matthias Sauer 002; Bernd Becker 001; Hans-Joachim Wunderlich (ETS, 2016)

SAT-Based Combinational and Sequential Dependency Computation. - Mathias Soeken; Pascal Raiola; Baruch Sterin; Bernd Becker 001; Giovanni De Micheli; Matthias Sauer 002 (Haifa Verification Conference, 2016)

Effective generation and evaluation of diagnostic SBST programs. - Andreas Riefert; Riccardo Cantoro; Matthias Sauer 002; Matteo Sonza Reorda; Bernd Becker 001 (VTS, 2016)

Extracting the RC4 secret key of the Open Smart Grid Protocol. - Linus Feiten; Matthias Sauer 002 (IACR Cryptol. ePrint Arch., 2016)

On Metrics to Quantify the Inter-Device Uniqueness of PUFs. - Linus Feiten; Matthias Sauer 002; Bernd Becker 001 (IACR Cryptol. ePrint Arch., 2016)

PHAETON: A SAT-Based Framework for Timing-Aware Path Sensitization. - Matthias Sauer 002; Bernd Becker 001; Ilia Polian (IEEE Trans. Computers, 2016)

Systemic Frequency Biases in Ring Oscillator PUFs on FPGAs. - Linus Feiten; Jonathan Oesterle; Tobias Martin; Matthias Sauer 002; Bernd Becker 001 (IEEE Trans. Multi Scale Comput. Syst., 2016)

A Flexible Framework for the Automatic Generation of SBST Programs. - Andreas Riefert; Riccardo Cantoro; Matthias Sauer 002; Matteo Sonza Reorda; Bernd Becker 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Sensitized path PUF: A lightweight embedded physical unclonable function. - Matthias Sauer 002; Pascal Raiola; Linus Feiten; Bernd Becker 001; Ulrich Rührmair; Ilia Polian (DATE, 2017)

Specification and verification of security in reconfigurable scan networks. - Michael A. Kochte; Matthias Sauer 002; Laura Rodríguez Gómez; Pascal Raiola; Bernd Becker 001; Hans-Joachim Wunderlich (ETS, 2017)

Online prevention of security violations in reconfigurable scan networks. - Ahmed Atteya; Michael A. Kochte; Matthias Sauer 002; Pascal Raiola; Bernd Becker 001; Hans-Joachim Wunderlich (ETS, 2018)

Towards the formal verification of security properties of a Network-on-Chip router. - Johanna Sepúlveda; Damian Aboul-Hassan; Georg Sigl; Bernd Becker 001; Matthias Sauer 002 (ETS, 2018)

Detecting and Resolving Security Violations in Reconfigurable Scan Networks. - Pascal Raiola; Michael A. Kochte; Ahmed Atteya; Laura Rodríguez Gómez; Hans-Joachim Wunderlich; Bernd Becker 001; Matthias Sauer 002 (IOLTS, 2018)

Efficient generation of parametric test conditions for AMS chips with an interval constraint solver. - Felix Neubauer; Jan Burchard; Pascal Raiola; Jochen Rivoir; Bernd Becker 001; Matthias Sauer 002 (VTS, 2018)

On Secure Data Flow in Reconfigurable Scan Networks. - Pascal Raiola; Benjamin Thiemann; Jan Burchard; Ahmed Atteya; Natalia Lylina; Hans-Joachim Wunderlich; Bernd Becker 001; Matthias Sauer 002 (DATE, 2019)

On Integrating Lightweight Encryption in Reconfigurable Scan Networks. - Benjamin Thiemann; Linus Feiten; Pascal Raiola; Bernd Becker 001; Matthias Sauer 002 (ETS, 2019)

Security Compliance Analysis of Reconfigurable Scan Networks. - Natalia Lylina; Ahmed Atteya; Pascal Raiola; Matthias Sauer 002; Bernd Becker 001; Hans-Joachim Wunderlich (ITC, 2019)

Exploring the Mysteries of System-Level Test. - Ilia Polian; Jens Anders; Steffen Becker 001; Paolo Bernardi; Krishnendu Chakrabarty; Nourhan Elhamawy; Matthias Sauer 002; Adit D. Singh; Matteo Sonza Reorda; Stefan Wagner 001 (ATS, 2020)

Security, Reliability and Test Aspects of the RISC-V Ecosystem. - Jaume Abella 001; Sergi Alcaide; Jens Anders; Francisco Bas; Steffen Becker 001; Elke De Mulder; Nourhan Elhamawy; Frank K. Gürkaynak; Helena Handschuh; Carles Hernández 001; Michael Hutter; Leonidas Kosmidis; et al. (ETS, 2021)

System-Level Test: State of the Art and Challenges. - Davide Appello; H. H. Chen; Matthias Sauer 002; Ilia Polian; Paolo Bernardi; Matteo Sonza Reorda (IOLTS, 2021)

New Techniques for the Automatic Identification of Uncontrollable Lines in a CPU Core. - Nikolaos Ioannis Deligiannis; Riccardo Cantoro; Matthias Sauer 002; Bernd Becker 001; Matteo Sonza Reorda (VTS, 2021)

Intelligent Methods for Test and Reliability. - Hussam Amrouch; Jens Anders; Steffen Becker 001; Maik Betka; Gerd Bleher; Peter Domanski; Nourhan Elhamawy; Thomas Ertl; Athanasios Gatzastras; Paul R. Genssler; Sebastian Hasler; Martin Heinrich; et al. (DATE, 2022)

Machine Learning for Test, Diagnosis, Post-Silicon Validation and Yield Optimization. - Hussam Amrouch; Krishnendu Chakrabarty; Dirk Pflüger; Ilia Polian; Matthias Sauer 002; Matteo Sonza Reorda (ETS, 2022)

A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors. - Jens Anders; Pablo Andreu; Bernd Becker 001; Steffen Becker 001; Riccardo Cantoro; Nikolaos Ioannis Deligiannis; Nourhan Elhamawy; Tobias Faller; Carles Hernández 001; Nele Mentens; Mahnaz Namazi Rizi; Ilia Polian; et al. (ETS, 2023)

Automating Greybox System-Level Test Generation. - Denis Schwachhofer; Maik Betka; Steffen Becker 001; Stefan Wagner 001; Matthias Sauer 002; Ilia Polian (ETS, 2023)

Large Language Model-Based Optimization for System-Level Test Program Generation. - Denis Schwachhofer; Peter Domanski; Steffen Becker 001; Stefan Wagner 001; Matthias Sauer 002; Dirk Pflüger; Ilia Polian (DFT, 2024)

Optimizing System-Level Test Program Generation via Genetic Programming. - Denis Schwachhofer; Francesco Angione; Steffen Becker 001; Stefan Wagner 001; Matthias Sauer 002; Paolo Bernardi; Ilia Polian (ETS, 2024)

Training Large Language Models for System-Level Test Program Generation Targeting Non-functional Properties. - Denis Schwachhofer; Peter Domanski; Steffen Becker 001; Stefan Wagner 001; Matthias Sauer 002; Dirk Pflüger; Ilia Polian (ETS, 2024)

Scenario-based Test Content Optimization: Scan Test vs. System-Level Test. - Nourhan Elhamawy; Jens Anders; Ilia Polian; Matthias Sauer 002 (VTS, 2024)

Large Language Models to Generate System-Level Test Programs Targeting Non-functional Properties. - Denis Schwachhofer; Peter Domanski; Steffen Becker 001; Stefan Wagner 001; Matthias Sauer 002; Dirk Pflüger; Ilia Polian (CoRR, 2024)

Towards Understanding of System-Level Test Unique Fails. - Nourhan Elhamawy; Jens Anders; Ilia Polian; Matthias Sauer 002 (ETS, 2025)

Automated Test Equipment Drift Characterization Based on Gauge Repeatability and Reproducibility. - Anand Venkatachalam; Ernst Aderholz; Matthias Sauer 002; Simon Schweizer; Matthias Werner; Ilia Polian (ETS, 2025)