Benchmarking micro-core architectures for detecting disasters at the edge. - Maurice Jamieson; Nick Brown 002 (UrgentHPC@SC, 2020)

Having your cake and eating it: Exploiting Python for programmer productivity and performance on micro-core architectures using ePython. - Maurice Jamieson; Nick Brown 002; Sihang Liu 004 (SciPy, 2020)

High level programming abstractions for leveraging hierarchical memories with micro-core architectures. - Maurice Jamieson; Nick Brown 002 (J. Parallel Distributed Comput., 2020)

Compact native code generation for dynamic languages on micro-core architectures. - Maurice Jamieson; Nick Brown 002 (CC, 2021)

Performance of the Vipera Framework for DSLs on Micro-Core Architectures. - Maurice Jamieson; Nick Brown 002 (Euro-Par Workshops, 2022)

Fortran performance optimisation and auto-parallelisation by leveraging MLIR-based domain specific abstractions in Flang. - Nick Brown 002; Maurice Jamieson; Anton Lydike; Emilien Bauer; Tobias Grosser (SC Workshops, 2023)

Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU. - Nick Brown 002; Maurice Jamieson; Joseph K. L. Lee; Paul Wang (SC Workshops, 2023)

Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGA. - Gabriel Rodriguez-Canal; Nick Brown 002; Maurice Jamieson; Emilien Bauer; Anton Lydike; Tobias Grosser (SC Workshops, 2023)

Backporting RISC-V Vector Assembly. - Joseph K. L. Lee; Maurice Jamieson; Nick Brown 002 (ISC Workshops, 2023)

Test-Driving RISC-V Vector Hardware for HPC. - Joseph K. L. Lee; Maurice Jamieson; Nick Brown 002; Ricardo Jesus (ISC Workshops, 2023)

Experiences of running an HPC RISC-V testbed. - Nick Brown 002; Maurice Jamieson; Joseph K. L. Lee (CoRR, 2023)

A shared compilation stack for distributed-memory parallelism in stencil DSLs. - George Bisbas; Anton Lydike; Emilien Bauer; Nick Brown 002; Mathieu Fehr; Lawrence Mitchell; Gabriel Rodriguez-Canal; Maurice Jamieson; Paul H. J. Kelly; Michel Steuwer; Tobias Grosser (ASPLOS (3), 2024)

Performance Characterisation of the 64-Core SG2042 RISC-V CPU for HPC. - Nick Brown 002; Maurice Jamieson (ISC Workshops, 2024)