FPGA Implementation of a GF(24M) Multiplier for use in Pairing Based Cryptosystems. - Maurice Keller; Tim Kerins; William P. Marnane (FPL, 2005)

FPGA Implementation of a GF(2m) Tate Pairing Architecture. - Maurice Keller; Tim Kerins; Francis M. Crowe; William P. Marnane (ARC, 2006)

A GF(24m) Inverter and its Application in a Reconfigurable Tate Pairing Processor. - Maurice Keller; Robert Ronan; William P. Marnane; Colin C. Murphy (ReConFig, 2006)

Low Power Elliptic Curve Cryptography. - Maurice Keller; William P. Marnane (PATMOS, 2007)

Hardware architectures for the Tate pairing over GF(2m). - Maurice Keller; Robert Ronan; William P. Marnane; Colin C. Murphy (Comput. Electr. Eng., 2007)

Energy Efficient Elliptic Curve Processor. - Maurice Keller; William P. Marnane (PATMOS, 2008)

A low-power pairing-based cryptographic accelerator for embedded security applications. - Tom English; Maurice Keller; Ka Lok Man; Emanuel M. Popovici; Michel P. Schellekens; William P. Marnane (SoCC, 2009)

Low Energy ASIC Elliptic Curve Processor. - Maurice Keller; William P. Marnane (J. Low Power Electron., 2009)

Elliptic Curve Cryptography on FPGA for Low-Power Applications. - Maurice Keller; Andrew Byrne; William P. Marnane (ACM Trans. Reconfigurable Technol. Syst., 2009)

Hardware Implementation of Pairings. - Maurice Keller; Robert Ronan; Andrew Byrne; Colin C. Murphy; William P. Marnane (Identity-Based Cryptography, 2009)

Network-on-Chip interconnect for pairing-based cryptographic IP cores. - Tom English; Emanuel M. Popovici; Maurice Keller; William P. Marnane (J. Syst. Archit., 2011)