Mauricio Alvarez

According to our database1, Mauricio Alvarez authored at least 38 papers between 2005 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2018
Highly parallel HEVC decoding for heterogeneous systems with CPU and GPU.
Sig. Proc.: Image Comm., 2018

PSNC advanced multimedia and visualization infrastructures, services and applications.
Proceedings of the 23rd International ACM Conference on 3D Web Technology, 2018

2017
GPU Parallelization of HEVC In-Loop Filters.
International Journal of Parallel Programming, 2017

Application-Specific Cache and Prefetching for HEVC CABAC Decoding.
IEEE MultiMedia, 2017

Syntax Element Partitioning for high-throughput HEVC CABAC decoding.
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

A Quantitative Analysis of the Memory Architecture of FPGA-SoCs.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

2016
An evaluation of current SIMD programming models for C++.
Proceedings of the 3rd Workshop on Programming Models for SIMD/Vector Processing, 2016

Efficient HEVC decoder for heterogeneous CPU with GPU systems.
Proceedings of the 18th IEEE International Workshop on Multimedia Signal Processing, 2016

2015
Parallel H.264/AVC Motion Compensation for GPUs Using OpenCL.
IEEE Trans. Circuits Syst. Video Techn., 2015

SIMD Acceleration for HEVC Decoding.
IEEE Trans. Circuits Syst. Video Techn., 2015

Spatiotemporal SIMT and Scalarization for Improving GPU Efficiency.
TACO, 2015

A parallel H.264/SVC encoder for high definition video conferencing.
Sig. Proc.: Image Comm., 2015

Reducing HEVC encoding complexity using two-stage motion estimation.
Proceedings of the 2015 Visual Communications and Image Processing, 2015

On latency in GPU throughput microarchitectures.
Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

Optimizing HEVC CABAC Decoding with a Context Model Cache and Application-Specific Prefetching.
Proceedings of the 2015 IEEE International Symposium on Multimedia, 2015

High Performance Memory Accesses on FPGA-SoCs: A Quantitative Analysis.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Multi/many-core programming: where are we standing?
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Low-Power High-Efficiency Video Decoding using General-Purpose Processors.
TACO, 2014

GPGPU workload characteristics and performance analysis.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

2013
Parallel HEVC Decoding on Multi- and Many-core Architectures - A Power and Performance Analysis.
Signal Processing Systems, 2013

How a single chip causes massive power bills GPUSimPow: A GPGPU power simulator.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

A low-complexity parallel-friendly rate control algorithm for ultra-low delay high definition video coding.
Proceedings of the 2013 IEEE International Conference on Multimedia and Expo Workshops, 2013

HEVC performance and complexity for 4K video.
Proceedings of the IEEE Third International Conference on Consumer Electronics, 2013

2012
Scalable Parallel Programming Applied to H.264/AVC Decoding.
Springer Briefs in Computer Science, Springer, ISBN: 978-1-4614-2230-3, 2012

Parallel Scalability and Efficiency of HEVC Parallelization Approaches.
IEEE Trans. Circuits Syst. Video Techn., 2012

Improving the parallelization efficiency of HEVC decoding.
Proceedings of the 19th IEEE International Conference on Image Processing, 2012

Parallel video decoding in the emerging HEVC standard.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

An Optimized Parallel IDCT on Graphics Processing Units.
Proceedings of the Euro-Par 2012: Parallel Processing Workshops, 2012

2011
A Highly Scalable Parallel Implementation of H.264.
Trans. HiPEAC, 2011

2010
The SARC Architecture.
IEEE Micro, 2010

2009
Parallel Scalability of Video Decoders.
Signal Processing Systems, 2009

Evaluación del rendimiento paralelo en el nivel macro bloque del decodificador H.264 en una arquitectura multiprocesador cc-NUMA.
RASI, 2009

Scalability of Macroblock-level Parallelism for H.264 Decoding.
Proceedings of the 15th IEEE International Conference on Parallel and Distributed Systems, 2009

Parallel H.264 Decoding on an Embedded Multicore Processor.
Proceedings of the High Performance Embedded Architectures and Compilers, 2009

2008
Analysis of video filtering on the cell processor.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Performance Impact of Unaligned Memory Operations in SIMD Extensions for Video Codec Applications.
Proceedings of the 2007 IEEE International Symposium on Performance Analysis of Systems and Software, 2007

HD-VideoBench. A Benchmark for Evaluating High Definition Digital Video Applications.
Proceedings of the IEEE 10th International Symposium on Workload Characterization, 2007

2005
On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005


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