NBTI-aware technique for transistor sizing of high-performance CMOS gates. - Maurício Banaszeski da Silva; Vinicius V. A. Camargo; Lucas Brusamarello; Gilson I. Wirth; Roberto da Silva (LATW, 2009)

Modeling the impact of RTS on the reliability of ring oscillators. - Maurício Banaszeski da Silva; Gilson I. Wirth (SBCCI, 2010)

Random Telegraph Noise in Analog CMOS Circuits. - Maurício Banaszeski da Silva; Gilson I. Wirth; Hans P. Tuinhout; Adrie Zegers-van Duijnhoven; Andries J. Scholten (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Modeling and Predicting Noise-Induced Failure Rates in Ultra-Low-Voltage SRAM Bitcells Affected by Process Variations. - Léopold Van Brandt; Michele Bonnin; Maurício Banaszeski da Silva; Pascal Bolcato; Gilson I. Wirth; Denis Flandre; Jean-Charles Delvenne (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)