Desarrollo de un Control Difuso de Temperatura para una Lámpara de Calor Radiante para Neonatos. - Jair Montoya; Juan Osorio; Mauricio Vanegas (CIIC, 2005)

Digital Hardware Design of a One-Dimensional Kohonen's SOFM with Chessboard Norm and Exponential Neighboring Function. - Jorge A. Peña; Andrés Valencia; Mauricio Vanegas (CIIC, 2005)

Digital Hardware Architectures of Kohonen's Self Organizing Feature Maps with Exponential Neighboring Function. - Jorge Peña 001; Mauricio Vanegas; Andrés Valencia (ReConFig, 2006)

Fine grain pipeline architecture for high performance phase-based optical flow computation. - Matteo Tomasi; Francisco Barranco; Mauricio Vanegas; Javier Díaz 001; Eduardo Ros Vidal (J. Syst. Archit., 2010)

Multi-port abstraction layer for FPGA intensive memory exploitation applications. - Mauricio Vanegas; Matteo Tomasi; Javier Díaz 001; Eduardo Ros Vidal (J. Syst. Archit., 2010)

High-Performance Optical-Flow Architecture Based on a Multi-Scale, Multi-Orientation Phase-Based Model. - Matteo Tomasi; Mauricio Vanegas; Francisco Barranco; Javier Díaz 001; Eduardo Ros 001 (IEEE Trans. Circuits Syst. Video Technol., 2010)

On-Chip Ego-Motion Estimation Based on Optical Flow. - Mauricio Vanegas; Leonardo Rubio; Matteo Tomasi; Javier Díaz 001; Eduardo Ros 001 (ARC, 2011)

Bio-inspired adaptive feedback error learning architecture for motor control. - Silvia Tolu; Mauricio Vanegas; Niceto R. Luque; Jesús Alberto Garrido; Eduardo Ros 001 (Biol. Cybern., 2012)

Massive Parallel-Hardware Architecture for Multiscale Stereo, Optical Flow and Image-Structure Computation. - Matteo Tomasi; Mauricio Vanegas; Francisco Barranco; Javier Díaz 001; Eduardo Ros 001 (IEEE Trans. Circuits Syst. Video Technol., 2012)

Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA. - Francisco Barranco; Matteo Tomasi; Javier Díaz 001; Mauricio Vanegas; Eduardo Ros 001 (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Real-Time Architecture for a Robust Multi-Scale Stereo Engine on FPGA. - Matteo Tomasi; Mauricio Vanegas; Francisco Barranco; Javier Díaz 001; Eduardo Ros 001 (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Pipelined architecture for real-time cost-optimized extraction of visual primitives based on FPGAs. - Francisco Barranco; Matteo Tomasi; Javier Díaz 001; Mauricio Vanegas; Eduardo Ros 001 (Digit. Signal Process., 2013)

Adaptive and Predictive Control of a Simulated Robot arm. - Silvia Tolu; Mauricio Vanegas; Jesús Alberto Garrido; Niceto R. Luque; Eduardo Ros 001 (Int. J. Neural Syst., 2013)

Hierarchical architecture for motion and depth estimations based on color cues. - Francisco Barranco; Matteo Tomasi; Mauricio Vanegas; Javier Díaz 001; Sara Granados; Eduardo Ros Vidal (J. Real Time Image Process., 2015)

A Portable Bio-Inspired Architecture for Efficient Robotic Vergence Control. - Agostino Gibaldi; Mauricio Vanegas; Andrea Canessa; Silvio P. Sabatini (Int. J. Comput. Vis., 2017)