JPEG 2000: finite precision representation and hardware implications. - Maurizio Martina; Guido Masera; Gianluca Piccinini; Fabrizio Vacca; Maurizio Zamboni (ICECS, 2001)

Reconfigurable coprocessor based JPEG 2000 implementation. - Maurizio Martina; Guido Masera; Gianluca Piccinini; Fabrizio Vacca; Maurizio Zamboni (ICECS, 2001)

Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor. - Maurizio Martina; Guido Masera; Gianluca Piccinini; Fabrizio Vacca; Maurizio Zamboni (FPL, 2002)

Reconfigurable DSP IP for multimedia applications. - Maurizio Martina; Guido Masera; Gianluca Piccinini; Fabrizio Vacca; Maurizio Zamboni (ICASSP, 2002)

System architecture for error-resilient, embedded JPEG2000 wireless delivery. - Maurizio Martina; Guido Masera; Gianluca Piccinini; Fabrizio Vacca; Maurizio Zamboni (DSP, 2002)

Embedded IWT evaluation in reconfigurable wireless sensor network. - Maurizio Martina; Guido Masera; Gianluca Piccinini; Fabrizio Vacca; Maurizio Zamboni (ICECS, 2002)

Reconfigurable and low power 2D-DCT IP for ubiquitous multimedia streaming. - Maurizio Martina; Andrea Molino; Fabrizio Vacca (ICME (2), 2002)

Optimization and implementation of the integer wavelet transform for image coding. - Marco Grangetto; Enrico Magli; Maurizio Martina; Gabriella Olmo (IEEE Trans. Image Process., 2002)

A reconfigurable, power-scalable rake receiver IP for W-CDMA. - A. Bianco; Alberto Dassatti; Maurizio Martina; Andrea Molino; Fabrizio Vacca (ASP-DAC, 2003)

Wireless sensor networks: a power-scalable motion estimation IP for hybrid video coding. - Federico Quaglio; Maurizio Martina; Fabrizio Vacca; Guido Masera; Andrea Molino; Gianluca Piccinini; Maurizio Zamboni (FPGA, 2003)

Design of a Power Conscious, Customizable CDMA Receiver. - Maurizio Martina; Andrea Molino; Mario Nicola; Fabrizio Vacca (FPL, 2003)

A Power-Scalable Motion Estimation Architecture for Energy Constrained Applications. - Maurizio Martina; Andrea Molino; Federico Quaglio; Fabrizio Vacca (FPL, 2003)

Implementation of a SPIHT coprocessor: memory issues and hardware implications. - Maurizio Martina; Andrea Molino; Andrea Terreno; Fabrizio Vacca (ICIP (2), 2003)

A power-scalable motion estimation coprocessor for energy constrained applications. - Maurizio Martina; Andrea Molino; Federico Quaglio; Fabrizio Vacca (ISSPA (2), 2003)

FPGA implementation of a reconfigurable SPIHT coprocessor. - Maurizio Martina; Andrea Molino; Andrea Terreno; Fabrizio Vacca (ISSPA (2), 2003)

Dynamic power scheduling system for JPEG2000 delivery over wireless networks. - Maurizio Martina; Fabrizio Vacca (VCIP, 2003)

Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations. - Maurizio Martina; Guido Masera; Gianluca Piccinini; Maurizio Zamboni (J. VLSI Signal Process., 2003)

A statistical model for estimating the effect of process variations on crosstalk noise. - Maurizio Martina; Guido Masera (SLIP, 2004)

System on chip. - Maurizio Martina (2004)

Low-complexity, efficient 9/7 wavelet filters implementation. - Maurizio Martina; Guido Masera (ICIP (3), 2005)

A new approach to compress the configuration information of programmable devices. - Maurizio Martina; Guido Masera; Andrea Molino; Fabrizio Vacca; Luca Sterpone; Massimo Violante (DATE Designers' Forum, 2006)

Hardware co-processors for Real-Time and High-Quality H.264/AVC video coding. - Maurizio Martina; Guido Masera; Luca Fanucci; Sergio Saponara (EUSIPCO, 2006)

Error correcting arithmetic coding for JPEG 2000: memory and performance analysis. - Simone Zezza; Marco Grangetto; Maurizio Martina; Fabrizio Vacca; Guido Masera (MobiMedia, 2006)

Mumford and Shah Functional: VLSI Analysis and Implementation. - Maurizio Martina; Guido Masera (IEEE Trans. Pattern Anal. Mach. Intell., 2006)

Low-Complexity, Efficient 9/7 Wavelet Filters VLSI Implementation. - Maurizio Martina; Guido Masera (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Flexible blocks for high throughput serially concatenated convolutional codes. - Maurizio Martina; Guido Masera (ACM Great Lakes Symposium on VLSI, 2007)

Real-time implementation of a time-frequency analysis scheme. - Maurizio Martina; Andrea Terreno; Fabrizio Vacca; Andrea Molino; Guido Masera; Giuseppe D'Angelo; Giorgio Pasquettaz (ACM Great Lakes Symposium on VLSI, 2007)

Multiplierless, Folded 9/7- 5/3 Wavelet VLSI Architecture. - Maurizio Martina; Guido Masera (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Error resilient JPEG2000 decoding for wireless applications. - Simone Zezza; Maurizio Martina; Guido Masera; Saeid Nooshabadi (ICIP, 2008)

Hardware design of a low complexity, parallel interleaver for WiMax duo-binary turbo decoding. - Maurizio Martina; Mario Nicola; Guido Masera (IEEE Commun. Lett., 2008)

Corrections to "Multiplierless, Folded 9/7-5/3 Wavelet VLSI Architecture" [Sep 07 770-774]. - Maurizio Martina; Guido Masera (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A Flexible UMTS-WiMax Turbo Decoder Architecture. - Maurizio Martina; Mario Nicola; Guido Masera (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

On Optimal and Near-Optimal Turbo Decoding Using Generalized max* Operator. - Stylianos Papaharalabos; P. Takis Mathiopoulos; Guido Masera; Maurizio Martina (IEEE Commun. Lett., 2009)

Vlsi Implementation of WiMAX Convolutional Turbo Code Encoder and Decoder. - Maurizio Martina; Mario Nicola; Guido Masera (J. Circuits Syst. Comput., 2009)

FPGA implementation of time-frequency analysis algorithms for laser welding monitoring. - Andrea Molino; Maurizio Martina; Fabrizio Vacca; Guido Masera; Andrea Terreno; Giorgio Pasquettaz; Giuseppe D'Angelo (Microprocess. Microsystems, 2009)

Efficient Implementation Techniques for Maximum Likelihood-Based Error Correction for JPEG2000. - Simone Zezza; Saeid Nooshabadi; Maurizio Martina; Guido Masera (IEEE Trans. Circuits Syst. Video Technol., 2009)

VLSI Architectures for WIMAX Channel Decoders - Maurizio Martina; Guido Masera (CoRR, 2010)

Scalable low-complexity B-spline discrete wavelet transform architecture. - Maurizio Martina; Guido Masera; Gianluca Piccinini (IET Circuits Devices Syst., 2010)

Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding. - Sergio Saponara; Maurizio Martina; Michele Casula; Luca Fanucci; Guido Masera (Microprocess. Microsystems, 2010)

Turbo NOC: A Framework for the Design of Network-on-Chip-Based Turbo Decoder Architectures. - Maurizio Martina; Guido Masera (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Multiplierless Mumford and Shah Functional Implementation. - Maurizio Martina; Guido Masera (Circuits Syst. Signal Process., 2011)

On chip interconnects for multiprocessor turbo decoding architectures. - Maurizio Martina; Guido Masera; Hazem Moussa; Amer Baghdadi (Microprocess. Microsystems, 2011)

State Metric Compression Techniques for Turbo Decoder Architectures. - Maurizio Martina; Guido Masera (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A Network-on-Chip-based turbo/LDPC decoder architecture. - Carlo Condo; Maurizio Martina; Guido Masera (DATE, 2012)

Reducing the memory for iteration-exchanged information and border future metrics in the HomePlug AV turbo decoder implementation. - Lorenzo Guerrieri; Paola Bisaglia; Maurizio Martina; Guido Masera (ISTC, 2012)

Non-recursive max* operator with reduced implementation complexity for turbo decoding. - Stylianos Papaharalabos; Panayiotis Takis Mathiopoulos; Guido Masera; Maurizio Martina (IET Commun., 2012)

An application specific instruction set processor based implementation for signal detection in multiple antenna systems. - M. Tamagnone; Maurizio Martina; Guido Masera (Microprocess. Microsystems, 2012)

An LDPC Decoder Architecture for Wireless Sensor Network Applications. - Andrea Dario Giancarlo Biroli; Maurizio Martina; Guido Masera (Sensors, 2012)

On Practical Implementation and Generalizations of max* Operator for Turbo and LDPC Decoders. - Maurizio Martina; Guido Masera; Stylianos Papaharalabos; P. Takis Mathiopoulos; Fotios Gioulekas (IEEE Trans. Instrum. Meas., 2012)

High Speed Architectures for Finding the First two Maximum/Minimum Values. - Luca Gaetano Amarù; Maurizio Martina; Guido Masera (IEEE Trans. Very Large Scale Integr. Syst., 2012)

VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards. - Maurizio Martina; Muhammad Shafique 001; Andrey Norkin (VLSI Design, 2012)

FPGA accelerator of Quasi cyclic EG-LDPC codes decoder for NAND flash memories. - Syed Azhar Ali Zaidi; Muhammad Awais 004; Carlo Condo; Maurizio Martina; Guido Masera (DASIP, 2013)

VLSI Architecture for Low-Complexity Motion Estimation in H.264 Multiview Video Coding. - Ashfaq Ahmed; Muhammad Usman Shahid; Maurizio Martina; Enrico Magli; Guido Masera (DSD, 2013)

VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture. - Carlo Condo; Maurizio Martina; Guido Masera (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Improving Network-on-Chip-based Turbo Decoder Architectures. - Maurizio Martina; Guido Masera (J. Signal Process. Syst., 2013)

Implementation of a Spread-Spectrum-Based Smart Lighting System on an Embedded Platform. - Maurizio Martina; Massimo Ruo Roch; Flavio Ghirardi (ApplePies, 2014)

Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-Based Applications. - Carlo Condo; Maurizio Martina; Massimo Ruo Roch; Guido Masera (PDP, 2014)

A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors. - Maurizio Martina; Carlo Condo; Guido Masera; Maurizio Zamboni (IEEE Embed. Syst. Lett., 2014)

Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced. - Carlo Condo; Maurizio Martina; Gianluca Piccinini; Guido Masera (IEEE Signal Process. Lett., 2014)

A Parallel Radix-Sort-Based VLSI Architecture for Finding the First W Maximum/Minimum Values. - Guoping Xiao; Maurizio Martina; Guido Masera; Gianluca Piccinini (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures. - Maurizio Martina; Stylianos Papaharalabos; P. Takis Mathiopoulos; Guido Masera (IEEE Trans. Instrum. Meas., 2014)

VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation. - Maurizio Awais; Guido Masera; Maurizio Martina; Guido Montorsi (IEEE Trans. Signal Process., 2014)

Optimizing the transform complexity-quality tradeoff for hardware-accelerated HEVC video coding. - Maurizio Masera; Lorenzo Re Fiorentin; Maurizio Martina; Guido Masera; Enrico Masala (DASIP, 2015)

An all-digital spike-based ultra-low-power IR-UWB dynamic average threshold crossing scheme for muscle force wireless transmission. - Masoud Shahshahani Amirhossein; Paolo Motto Ros; Alberto Bonanno; Marco Crepaldi; Maurizio Martina; Danilo Demarchi; Guido Masera (DATE, 2015)

Complexity and implementation analysis of synthesized view distortion estimation architecture in 3D High Efficiency Video Coding. - Waqar Ahmad; Maurizio Martina; Guido Masera (IC3D, 2015)

Using Information Centric Networking for Mobile Devices Cooperation at the Network Edge. - Fabio Malabocchia; Romeo Corgiolu; Maurizio Martina; Andrea Detti; Bruno Ricci; Nicola Blefari-Melazzi (VTC Spring, 2015)

Comments on "Bitwise Log-Likelihood Ratios for Quadrature Amplitude Modulations". - Stylianos Papaharalabos; P. Takis Mathiopoulos; Maurizio Martina; Guido Masera (IEEE Commun. Lett., 2015)

Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures. - Carlo Condo; Maurizio Martina; Massimo Ruo Roch; Guido Masera (Integr., 2015)

Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT. - Maurizio Martina; Guido Masera; Massimo Ruo Roch; Gianluca Piccinini (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Parallel H.264/AVC Fast Rate-Distortion Optimized Motion Estimation by Using a Graphics Processing Unit and Dedicated Hardware. - Muhammad Usman Shahid; Ashfaq Ahmed; Maurizio Martina; Guido Masera; Enrico Magli (IEEE Trans. Circuits Syst. Video Technol., 2015)

High Level Synthesis based FPGA Implementation of H.264/AVC Sub-Pixel Luma Interpolation Filters. - Waqar Ahmad; Javed Iqbal; Maurizio Martina; Guido Masera (EMS, 2016)

Comparison between HEVC and Thor based on objective and subjective assessments. - Lorenzo Re Fiorentin; Maurizio Masera; Sabino Mantovano; Paola Sunna; Guido Masera; Maurizio Martina (IWSSIP, 2016)

FPGA Accelerator of Algebraic Quasi Cyclic LDPC Codes for nand Flash Memories. - Syed Azhar Ali Zaidi; Abuduwaili Tuoheti; Maurizio Martina; Guido Masera (IEEE Des. Test, 2016)

A low power architecture for AER event-processing microcontroller. - Simone Aiassa; Paolo Motto Ros; Guido Masera; Maurizio Martina (BioCAS, 2017)

Low-Power Hardware Accelerator for Sparse Matrix Convolution in Deep Neural Network. - Erik Anzalone; Maurizio Capra; Riccardo Peloso; Maurizio Martina; Guido Masera (IIH-MSP (1), 2017)

Approximate Arai DCT Architecture for HEVC. - Giovanni Renda; Maurizio Masera; Maurizio Martina; Guido Masera (NGCAS, 2017)

Odd type DCT/DST for video coding: Relationships and low-complexity implementations. - Maurizio Masera; Maurizio Martina; Guido Masera (SiPS, 2017)

Analysis of HEVC transform throughput requirements for hardware implementations. - Maurizio Masera; Lorenzo Re Fiorentin; Enrico Masala; Guido Masera; Maurizio Martina (Signal Process. Image Commun., 2017)

Adaptive Approximated DCT Architectures for HEVC. - Maurizio Masera; Maurizio Martina; Guido Masera (IEEE Trans. Circuits Syst. Video Technol., 2017)

A Low Cost ALS and VLC Circuit for Solid State Lighting. - Massimo Ruo Roch; Maurizio Martina (ApplePies, 2018)

An Optimized Partial-Distortion-Elimination Based Sum-of-Absolute-Differences Architecture for High-Efficiency-Video-Coding. - Paolo Selvo; Maurizio Masera; Riccardo Peloso; Guido Masera; Muhammad Shafique 001; Maurizio Martina (ApplePies, 2018)

PruNet: Class-Blind Pruning Method For Deep Neural Networks. - Alberto Marchisio; Muhammad Abdullah Hanif; Maurizio Martina; Muhammad Shafique 001 (IJCNN, 2018)

Live Demonstration: Tactile Events from Off-The-Shelf Sensors in a Robotic Skin. - Chiara Bartolozzi; Paolo Motto Ros; Riccardo Peloso; Francesco Diotalevi; Marco Crepaldi; Maurizio Martina; Danilo Demarchi (ISCAS, 2018)

Approximate-Computing Architectures for Motion Estimation in HEVC. - Alberto Paltrinieri; Riccardo Peloso; Guido Masera; Muhammad Shafique 001; Maurizio Martina (NGCAS, 2018)

A Methodology for Automatic Selection of Activation Functions to Design Hybrid Deep Neural Networks. - Alberto Marchisio; Muhammad Abdullah Hanif; Semeen Rehman; Maurizio Martina; Muhammad Shafique 001 (CoRR, 2018)

Selected Articles from the NGCAS 2017 Conference. - Maurizio Valle; Ali Ibrahim; Maurizio Martina; Michele Magno (J. Low Power Electron., 2018)

Guest EditorialSpecial Issue on Selected Papers From IEEE BioCAS 2017. - Maurizio Martina; Fernando Corinto; Sandro Carrara (IEEE Trans. Biomed. Circuits Syst., 2018)

3D-HEVC Neighboring Block Based Disparity Vector (NBDV) Derivation Architecture: Complexity and Implementation Analysis. - Waqar Ahmad; Naveed Khan Baloch; Fawad Hussain; Muhammad Asif Khan 002; Maurizio Martina (ApplePies, 2019)

VLSI Architectures for the Steerable-Discrete-Cosine-Transform (SDCT). - Luigi Sole; Riccardo Peloso; Maurizio Capra; Massimo Ruo Roch; Guido Masera; Maurizio Martina (ApplePies, 2019)

Live Demonstration: Low Power Embedded System for Event-Driven Hand Gesture Recognition. - Andrea Mongardi; Fabio Rossi; Paolo Motto Ros; Alessandro Sanginario; Massimo Ruo Roch; Maurizio Martina; Danilo Demarchi (BioCAS, 2019)

A Novel Framework for Designing Directional Linear Transforms with Application to Video Compression. - Maurizio Masera; Giulia Fracastoro; Maurizio Martina; Enrico Magli (ICASSP, 2019)

Impulse-Based Asynchronous Serial Communication Protocol on Optical Fiber Link for AER Systems. - Andrea De Marcellis; Guido Di Patrizio Stanchieri; Paolo Motto Ros; Maurizio Martina; Danilo Demarchi; Chiara Bartolozzi; Marco Faccio; Elia Palange (ICECS, 2019)

A Low-Power Embedded System for Real-Time sEMG based Event-Driven Gesture Recognition. - Andrea Mongardi; Paolo Motto Ros; Fabio Rossi; Massimo Ruo Roch; Maurizio Martina; Danilo Demarchi (ICECS, 2019)

Live Demonstration: Event-Driven Serial Communication on Optical Fiber. - Andrea De Marcellis; Guido Di Patrizio Stanchieri; Marco Faccio; Elia Palange; Paolo Motto Ros; Maurizio Martina; Danilo Demarchi; Chiara Bartolozzi (ISCAS, 2019)

CapsAttacks: Robust and Imperceptible Adversarial Attacks on Capsule Networks. - Alberto Marchisio; Giorgio Nanfa; Faiq Khalid; Muhammad Abdullah Hanif; Maurizio Martina; Muhammad Shafique 001 (CoRR, 2019)

SNN under Attack: are Spiking Deep Belief Networks vulnerable to Adversarial Examples? - Alberto Marchisio; Giorgio Nanfa; Faiq Khalid; Muhammad Abdullah Hanif; Maurizio Martina; Muhammad Shafique 001 (CoRR, 2019)

X-TrainCaps: Accelerated Training of Capsule Nets through Lightweight Software Optimizations. - Alberto Marchisio; Beatrice Bussolino; Alessio Colucci; Muhammad Abdullah Hanif; Maurizio Martina; Guido Masera; Muhammad Shafique 001 (CoRR, 2019)

Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World. - Maurizio Capra; Riccardo Peloso; Guido Masera; Massimo Ruo Roch; Maurizio Martina (Future Internet, 2019)

On the Effect of Approximate-Computing in Motion Estimation. - Alberto Paltrinieri; Riccardo Peloso; Guido Masera; Muhammad Shafique 001; Maurizio Martina (J. Low Power Electron., 2019)

vrLab: A Virtual and Remote Low Cost Electronics Lab Platform. - Massimo Ruo Roch; Maurizio Martina (ApplePies, 2020)

A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress. - Alessio Colucci; Alberto Marchisio; Beatrice Bussolino; Vojtech Mrazek; Maurizio Martina; Guido Masera; Muhammad Shafique 001 (CODES+ISSS, 2020)

NACU: A Non-Linear Arithmetic Unit for Neural Networks. - Guido Baccelli; Dimitrios Stathis 001; Ahmed Hemani; Maurizio Martina (DAC, 2020)

Q-CapsNets: A Specialized Framework for Quantizing Capsule Networks. - Alberto Marchisio; Beatrice Bussolino; Alessio Colucci; Maurizio Martina; Guido Masera; Muhammad Shafique 001 (DAC, 2020)

NASCaps: A Framework for Neural Architecture Search to Optimize the Accuracy and Hardware Efficiency of Convolutional Capsule Networks. - Alberto Marchisio; Andrea Massa; Vojtech Mrazek; Beatrice Bussolino; Maurizio Martina; Muhammad Shafique 001 (ICCAD, 2020)

FasTrCaps: An Integrated Framework for Fast yet Accurate Training of Capsule Networks. - Alberto Marchisio; Beatrice Bussolino; Alessio Colucci; Muhammad Abdullah Hanif; Maurizio Martina; Guido Masera; Muhammad Shafique 001 (IJCNN, 2020)

Is Spiking Secure? A Comparative Study on the Security Vulnerabilities of Spiking and Deep Neural Networks. - Alberto Marchisio; Giorgio Nanfa; Faiq Khalid; Muhammad Abdullah Hanif; Maurizio Martina; Muhammad Shafique 001 (IJCNN, 2020)

An Efficient Spiking Neural Network for Recognizing Gestures with a DVS Camera on the Loihi Neuromorphic Processor. - Riccardo Massa; Alberto Marchisio; Maurizio Martina; Muhammad Shafique 001 (IJCNN, 2020)

NeuroAttack: Undermining Spiking Neural Networks Security through Externally Triggered Bit-Flips. - Valerio Venceslai; Alberto Marchisio; Ihsen Alouani; Maurizio Martina; Muhammad Shafique 001 (IJCNN, 2020)

Towards Optimal Green Plant Irrigation: Watering and Body Electrical Impedance. - Umberto Garlando; Lee Bar-on; Paolo Motto Ros; Alessandro Sanginario; Sebastian Peradotto; Yosi Shacham-Diamand; Adi Avni; Maurizio Martina; Danilo Demarchi (ISCAS, 2020)

A Hardware Implementation for Code-based Post-quantum Asymmetric Cryptography. - Kristjane Koleci; Marco Baldi; Maurizio Martina; Guido Masera (ITASEC, 2020)

Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead. - Maurizio Capra; Beatrice Bussolino; Alberto Marchisio; Guido Masera; Maurizio Martina; Muhammad Shafique 001 (IEEE Access, 2020)

An Updated Survey of Efficient Hardware Architectures for Accelerating Deep Convolutional Neural Networks. - Maurizio Capra; Beatrice Bussolino; Alberto Marchisio; Muhammad Shafique 001; Guido Masera; Maurizio Martina (Future Internet, 2020)

Guest editorial: Special issue on intelligent embedded systems architectures and applications (INTESA). - Maurizio Martina; William Fornaciari (Microprocess. Microsystems, 2020)

Assessing the Feasibility of Augmenting Fall Detection Systems by Relying on UWB-Based Position Tracking and a Home Robot. - Maurizio Capra; Stefano Sapienza; Paolo Motto Ros; Alessio Serrani; Maurizio Martina; Alessandro Puiatti; Paolo Bonato; Danilo Demarchi (Sensors, 2020)

Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis. - Riccardo Peloso; Maurizio Capra; Luigi Sole; Massimo Ruo Roch; Guido Masera; Maurizio Martina (Sensors, 2020)

Low-Complexity Reconfigurable DCT-V Architecture. - Jurgen Kello; Massimo Ruo Roch; Guido Masera; Maurizio Martina (IEEE Trans. Circuits Syst., 2020)

An Area-Efficient Variable-Size Fixed-Point DCT Architecture for HEVC Encoding. - Maurizio Masera; Guido Masera; Maurizio Martina (IEEE Trans. Circuits Syst. Video Technol., 2020)

A Low Cost Compact Output Amplifier for Multichannel Muscle Stimulation. - Massimo Ruo Roch; Maurizio Martina (ApplePies, 2021)

Live Demonstration: Event-Driven Hand Gesture Recognition for Wearable Human-Machine Interface. - Martina Becchio; Niccoló Voster; Andrea Prestia; Andrea Mongardi; Fabio Rossi; Paolo Motto Ros; Massimo Ruo Roch; Maurizio Martina; Danilo Demarchi (BioCAS, 2021)

Low Latency Protocols Investigation for Event-Driven Wireless Body Area Networks. - Andrea Mongardi; Fabio Rossi; Elia Pellegrino; Paolo Motto Ros; Massimo Ruo Roch; Maurizio Martina (BioCAS, 2021)

Very Low Latency Architecture for Earth Observation Satellite Onboard Data Handling, Compression, and Encryption. - Michele Caon; Paolo Motto Ros; Maurizio Martina; Tiziano Bianchi; Enrico Magli; Francisco Membibre; Alexis Ramos; Antonio Latorre; Murray Kerr; Stefan Wiehle; Helko Breit; Dominik Günzel; et al. (IGARSS, 2021)

High-Level Synthesis of a Single/Multi-Band Optical and SAR Image Compression and Encryption Hardware Accelerator. - Paolo Motto Ros; Michele Caon; Tiziano Bianchi; Maurizio Martina; Enrico Magli (IGARSS, 2021)

DVS-Attacks: Adversarial Attacks on Dynamic Vision Sensors for Spiking Neural Networks. - Alberto Marchisio; Giacomo Pira; Maurizio Martina; Guido Masera; Muhammad Shafique 001 (IJCNN, 2021)

CarSNN: An Efficient Spiking Neural Network for Event-Based Autonomous Cars on the Loihi Neuromorphic Research Processor. - Alberto Viale; Alberto Marchisio; Maurizio Martina; Guido Masera; Muhammad Shafique 001 (IJCNN, 2021)

R-SNN: An Analysis and Design Methodology for Robustifying Spiking Neural Networks against Adversarial Attacks through Noise Filters for Dynamic Vision Sensors. - Alberto Marchisio; Giacomo Pira; Maurizio Martina; Guido Masera; Muhammad Shafique 001 (IROS, 2021)

Analysis of in Vivo Plant Stem Impedance Variations in Relation with External Conditions Daily Cycle. - Umberto Garlando; Lee Bar-On; Paolo Motto Ros; Alessandro Sanginario; Stefano Calvo; Maurizio Martina; Adi Avni; Yosi Shacham-Diamand; Danilo Demarchi (ISCAS, 2021)

A Multi-Precision Bit-Serial Hardware Accelerator IP for Deep Learning Enabled Internet-of-Things. - Maurizio Capra; Francesco Conti 001; Maurizio Martina (MWSCAS, 2021)

Efficient Hardware Implementation of the LEDAcrypt Decoder. - Kristjane Koleci; Paolo Santini; Marco Baldi; Franco Chiaraluce; Maurizio Martina; Guido Masera (IEEE Access, 2021)

Real-time implementation of fast discriminative scale space tracking algorithm. - Walid Walid; Muhammad Awais 004; Ashfaq Ahmed; Guido Masera; Maurizio Martina (J. Real Time Image Process., 2021)

Smart Portable Pen for Continuous Monitoring of Anaesthetics in Human Serum With Machine Learning. - Simone Aiassa; Paolo Motto Ros; Ivan Ny Hanitra; Davide Tunzi; Maurizio Martina; Sandro Carrara; Danilo Demarchi (IEEE Trans. Biomed. Circuits Syst., 2021)

HW-FlowQ: A Multi-Abstraction Level HW-CNN Co-design Quantization Methodology. - Nael Fasfous; Manoj Rohit Vemparala; Alexander Frickenstein; Emanuele Valpreda; Driton Salihu; Nguyen Anh Vu Doan; Christian Unger; Naveen Shankar Nagaraja; Maurizio Martina; Walter Stechele (ACM Trans. Embed. Comput. Syst., 2021)

A Side Channel Attack Methodology Applied to Code-Based Post Quantum Cryptography. - Kristjane Koleci; Lorenzo Cecchetti; Guido Masera; Maurizio Martina; Massimo Ruo Roch (ApplePies, 2022)

Mind the Scaling Factors: Resilience Analysis of Quantized Adversarially Robust CNNs. - Nael Fasfous; Lukas Frickenstein; Michael Neumeier; Manoj Rohit Vemparala; Alexander Frickenstein; Emanuele Valpreda; Maurizio Martina; Walter Stechele (DATE, 2022)

AnaCoNGA: Analytical HW-CNN Co-Design Using Nested Genetic Algorithms. - Nael Fasfous; Manoj Rohit Vemparala; Alexander Frickenstein; Emanuele Valpreda; Driton Salihu; Julian Höfer; Anmol Singh; Naveen Shankar Nagaraja; Hans-Jörg Vögel; Nguyen Anh Vu Doan; Maurizio Martina; Jürgen Becker 001; et al. (DATE, 2022)

NLCMAP: A Framework for the Efficient Mapping of Non-Linear Convolutional Neural Networks on FPGA Accelerators. - Giuseppe Aiello; Beatrice Bussolino; Emanuele Valpreda; Massimo Ruo Roch; Guido Masera; Maurizio Martina; Stefano Marsi (ICIP, 2022)

CoNLoCNN: Exploiting Correlation and Non-Uniform Quantization for Energy-Efficient Low-precision Deep Convolutional Neural Networks. - Muhammad Abdullah Hanif; Giuseppe Maria Sarda; Alberto Marchisio; Guido Masera; Maurizio Martina; Muhammad Shafique 001 (IJCNN, 2022)

fakeWeather: Adversarial Attacks for Deep Neural Networks Emulating Weather Conditions on the Camera Lens of Autonomous Systems. - Alberto Marchisio; Giovanni Caramia; Maurizio Martina; Muhammad Shafique 001 (IJCNN, 2022)

LaneSNNs: Spiking Neural Networks for Lane Detection on the Loihi Neuromorphic Processor. - Alberto Viale; Alberto Marchisio; Maurizio Martina; Guido Masera; Muhammad Shafique 001 (IROS, 2022)

Enabling Capsule Networks at the Edge through Approximate Softmax and Squash Operations. - Alberto Marchisio; Beatrice Bussolino; Edoardo Salvati; Maurizio Martina; Guido Masera; Muhammad Shafique 001 (ISLPED, 2022)

RoHNAS: A Neural Architecture Search Framework With Conjoint Optimization for Adversarial Robustness and Hardware Efficiency of Convolutional and Capsule Networks. - Alberto Marchisio; Vojtech Mrazek; Andrea Massa; Beatrice Bussolino; Maurizio Martina; Muhammad Shafique 001 (IEEE Access, 2022)

AccelAT: A Framework for Accelerating the Adversarial Training of Deep Neural Networks Through Accuracy Gradient. - Farzad Nikfam; Alberto Marchisio; Maurizio Martina; Muhammad Shafique 001 (IEEE Access, 2022)

HW-Flow: A Multi-Abstraction Level HW-CNN Codesign Pruning Methodology. - Manoj Rohit Vemparala; Nael Fasfous; Alexander Frickenstein; Emanuele Valpreda; Manfredi Camalleri; Qi Zhao; Christian Unger; Naveen Shankar Nagaraja; Maurizio Martina; Walter Stechele (Leibniz Trans. Embed. Syst., 2022)

VirtLAB: A Low-Cost Platform for Electronics Lab Experiments. - Massimo Ruo Roch; Maurizio Martina (Sensors, 2022)

Motion Analysis for Experimental Evaluation of an Event-Driven FES System. - Andrea Prestia; Fabio Rossi; Andrea Mongardi; Paolo Motto Ros; Massimo Ruo Roch; Maurizio Martina; Danilo Demarchi (IEEE Trans. Biomed. Circuits Syst., 2022)

Hand Gestures Recognition for Human-Machine Interfaces: A Low-Power Bio-Inspired Armband. - Andrea Mongardi; Fabio Rossi; Andrea Prestia; Paolo Motto Ros; Massimo Ruo Roch; Maurizio Martina; Danilo Demarchi (IEEE Trans. Biomed. Circuits Syst., 2022)

LOKI Low-Latency Open-Source Kyber-Accelerator IPs. - Alessandra Dolmeta; Mattia Mirigaldi; Maurizio Martina; Guido Masera (ApplePies, 2023)

TEMET: Truncated REconfigurable Multiplier with Error Tuning. - Flavia Guella; Emanuele Valpreda; Michele Caon; Guido Masera; Maurizio Martina (ApplePies, 2023)

A Low Cost Open Platform for Development and Performance Evaluation of IoT and IIoT Systems. - Massimo Ruo Roch; Maurizio Martina (ApplePies, 2023)

Implementation and integration of Keccak accelerator on RISC-V for CRYSTALS-Kyber. - Alessandra Dolmeta; Mattia Mirigaldi; Maurizio Martina; Guido Masera (CF, 2023)

SwiftTron: An Efficient Hardware Accelerator for Quantized Transformers. - Alberto Marchisio; Davide Dura; Maurizio Capra; Maurizio Martina; Guido Masera; Muhammad Shafique 001 (IJCNN, 2023)

RobCaps: Evaluating the Robustness of Capsule Networks against Affine Transformations and Adversarial Attacks. - Alberto Marchisio; Antonio De Marco; Alessio Colucci; Maurizio Martina; Muhammad Shafique 001 (IJCNN, 2023)

Hardware architecture for CRYSTALS-Kyber post-quantum cryptographic SHA-3 primitives. - Alessandra Dolmeta; Maurizio Martina; Guido Masera (PRIME, 2023)

ERODE: Error Resilient Object DetEction by Recovering Bounding Box and Class Information. - Emanuele Valpreda; Giuseppe Palumbo; Michele Caon; Guido Masera; Maurizio Martina (PRIME, 2023)

RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project. - William Fornaciari; Federico Reghenzani; Giovanni Agosta; Davide Zoni; Andrea Galimberti; Francesco Conti 001; Yvan Tortorella; Emanuele Parisi; Francesco Barchi; Andrea Bartolini; Andrea Acquaviva; Daniele Gregori; et al. (SAMOS, 2023)

A Flexible NTT-Based Multiplier for Post-Quantum Cryptography. - Kristjane Koleci; Paolo Mazzetti; Maurizio Martina; Guido Masera (IEEE Access, 2023)

A Homomorphic Encryption Framework for Privacy-Preserving Spiking Neural Networks. - Farzad Nikfam; Raffaele Casaburi; Alberto Marchisio; Maurizio Martina; Muhammad Shafique 001 (Inf., 2023)

Architectural Comparison Model for Area-Efficient PMAP Turbo-Decoders. - Simone Favero; Maurizio Martina; Guido Masera (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

SeVuc: A study on the Security Vulnerabilities of Capsule Networks against adversarial attacks. - Alberto Marchisio; Giorgio Nanfa; Faiq Khalid; Muhammad Abdullah Hanif; Maurizio Martina; Muhammad Shafique 001 (Microprocess. Microsystems, 2023)

Comparative Study of Keccak SHA-3 Implementations. - Alessandra Dolmeta; Maurizio Martina; Guido Masera (Cryptogr., 2023)

Exploring the New CV-X-IF Interface to Customize RISC-V Instruction Sets: A Case of Study in Cryptography. - Alessandra Dolmeta; Maurizio Martina; Guido Masera (ApplePies, 2024)

Performance Comparison: Software vs. Hardware Implementation of Novel S-Box Designed to Resist Power Analysis Attack. - Mattia Mirigaldi; Maurizio Martina; Guido Masera (ApplePies, 2024)

Seeing Beyond the Order: a LEN5 to Sharpen Edge Microprocessors with Dynamic Scheduling. - Michele Caon; Vincenzo Petrolo; Mattia Mirigaldi; Flavia Guella; Guido Masera; Maurizio Martina (CF (Companion), 2024)

Performance evaluation of acceleration of convolutional layers on OpenEdgeCGRA. - Nicolò Carpentieri; Juan Sapriza; Pasquale Davide Schiavone; Daniele Jahier Pagliari; David Atienza; Maurizio Martina; Alessio Burrello (CF (Companion), 2024)

Implementation and integration of NTT/INTT accelerator on RISC-V for CRYSTALS-Kyber. - Alessandra Dolmeta; Emanuele Valpreda; Maurizio Martina; Guido Masera (CF (Companion), 2024)

VirtLAB-UI: An Open, Platform Independent, Software and Firmware Solution for Remote and Take-Home Labs. - Massimo Ruo Roch; Maurizio Martina (EDUCON, 2024)

A Case Study on Formal Equivalence Verification Between a C/C++ Model and Its RTL Design. - Gaetano Raia; Gianluca Rigano; David Vincenzoni; Maurizio Martina (FM (2), 2024)

ATHOS: A Hybrid Accelerator for PQC CRYSTALS-Algorithms Exploiting New CV-X-IF Interface. - Alessandra Dolmeta; Maurizio Martina; Guido Masera (IEEE Access, 2024)

TinyCL: An Efficient Hardware Architecture for Continual Learning on Autonomous Systems. - Eugenio Ressa; Alberto Marchisio; Maurizio Martina; Guido Masera; Muhammad Shafique 001 (CoRR, 2024)

Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes. - Michele Caon; Clément Choné; Pasquale Davide Schiavone; Alexandre Levisse; Guido Masera; Maurizio Martina; David Atienza (CoRR, 2024)

MARLIN: A Co-Design Methodology for Approximate ReconfigurabLe Inference of Neural Networks at the Edge. - Flavia Guella; Emanuele Valpreda; Michele Caon; Guido Masera; Maurizio Martina (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Stop Wasting your Cache! Bringing Machine Learning into Cache Computing. - Vincenzo Petrolo; Flavia Guella; Michele Caon; Guido Masera; Maurizio Martina (CF (Companion), 2025)

A Deep Dive into Integration Methodologies in RISC-V. - Valeria Piscopo; Alessandra Dolmeta; Mattia Mirigaldi; Maurizio Martina; Guido Masera (CF (Companion), 2025)

Just TestIt! An SBST Approach To Automate System-Integration Testing. - Tommaso Terzano; Luigi Giuffrida; Juan Sapriza; Pasquale Davide Schiavone; Guido Masera; David Atienza; Luciano Lavagno; Maurizio Martina (CF (Companion), 2025)

TYRCA: A RISC-V Tightly-Coupled Accelerator for Code-Based Cryptography. - Alessandra Dolmeta; Stefano Di Matteo; Emanuele Valea; Mikael Carmona; Antoine Loiseau; Maurizio Martina; Guido Masera (DATE, 2025)

RISC-V Based Keccak Co-Processor for NIST Post-Quantum Cryptography Standards. - Alessandra Dolmeta; Valeria Piscopo; Mattia Mirigaldi; Maurizio Martina; Guido Masera (ISCAS, 2025)

CHIMERA: Cryptographic Hardware for Integrated Multipurpose Engine on RISC-V with ASCON. - Alessandra Dolmeta; Valeria Piscopo; Maurizio Martina; Guido Masera (ISVLSI, 2025)

ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions. - Vincenzo Petrolo; Flavia Guella; Michele Caon; Pasquale Davide Schiavone; Guido Masera; Maurizio Martina (CoRR, 2025)