Parameterised system design based on genetic algorithms. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi (CODES, 2001)

An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi (VLSI-SOC, 2001)

An Instruction-Level Power Analysis Model with Data Dependency. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi; Davide Sarta (VLSI Design, 2001)

Multi-objective design space exploration using genetic algorithms. - Maurizio Palesi; Tony Givargis (CODES, 2002)

A Framework for Design Space Exploration of Parameterized VLSI Systems. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi (ASP-DAC/VLSI Design, 2002)

An evolutionary approach for reducing the switching activity in address buses. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi; Antonio Parlato (IEEE Congress on Evolutionary Computation, 2003)

EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi; Davide Patti (ESTIMedia, 2003)

An evolutionary approach for reducing the energy in address buses. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi; Antonio Parlato (ISICT, 2003)

A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi (PATMOS, 2003)

A Genetic Approach To Bus Encoding. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi (VLSI-SOC, 2003)

Multi-objective mapping for mesh-based NoC architectures. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi (CODES+ISSS, 2004)

Multi-objective Optimization of a Parameterized VLIW Architecture. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi; Davide Patti (Evolvable Hardware, 2004)

A GA-based design space exploration framework for parameterized system-on-a-chip platforms. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi (IEEE Trans. Evol. Comput., 2004)

Exploring Design Space of VLIW Architectures. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi; Davide Patti (ASAP, 2005)

A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi; Davide Patti (ASP-DAC, 2005)

An evolutionary approach to network-on-chip mapping problem. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi (Congress on Evolutionary Computation, 2005)

Hyperblock formation: a power/energy perspective for high performance VLIW architectures. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi; Davide Patti (ISCAS (4), 2005)

A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design. - Giuseppe Ascia; Vincenzo Catania; Alessandro G. Di Nuovo; Maurizio Palesi; Davide Patti (IEEE Congress on Evolutionary Computation, 2006)

Fuzzy decision making in embedded system design. - Alessandro G. Di Nuovo; Maurizio Palesi; Davide Patti; Giuseppe Ascia; Vincenzo Catania (CODES+ISSS, 2006)

A methodology for design of application specific deadlock-free routing algorithms for NoC systems. - Maurizio Palesi; Rickard Holsmark; Shashi Kumar; Vincenzo Catania (CODES+ISSS, 2006)

Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions. - Rickard Holsmark; Maurizio Palesi; Shashi Kumar (DSD, 2006)

Neighbors-on-Path: A New Selection Strategy for On-Chip Networks. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi; Davide Patti (ESTIMedia, 2006)

An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design. - Giuseppe Ascia; Vincenzo Catania; Alessandro G. Di Nuovo; Maurizio Palesi; Davide Patti (ICSAMOS, 2006)

A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures. - Maurizio Palesi; Shashi Kumar; Rickard Holsmark (SAMOS, 2006)

An Hybrid Soft Computing Approach for Automated Computer Design. - Alessandro G. Di Nuovo; Maurizio Palesi; Davide Patti (STAIRS, 2006)

A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi (J. Univers. Comput. Sci., 2006)

Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems. - Alessandro G. Di Nuovo; Maurizio Palesi; Vincenzo Catania (FUZZ-IEEE, 2007)

Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms. - Maurizio Palesi; Shashi Kumar; Rickard Holsmark; Vincenzo Catania (IPDPS, 2007)

Analysis and Tools for the Design of VLIW Embedded Systems in a Multi-Objective Scenario. - Vincenzo Catania; Maurizio Palesi; Davide Patti (J. Circuits Syst. Comput., 2007)

Efficient design space exploration for application specific systems-on-a-chip. - Giuseppe Ascia; Vincenzo Catania; Alessandro G. Di Nuovo; Maurizio Palesi; Davide Patti (J. Syst. Archit., 2007)

Networks-on-Chip: Emerging Research Topics and Novel Ideas. - Davide Bertozzi; Shashi Kumar; Maurizio Palesi (VLSI Design, 2007)

High Performance Computing for Embedded System Design: A Case Study. - Vincenzo Catania; Gianmarco De Francisci Morales; Alessandro G. Di Nuovo; Maurizio Palesi; Davide Patti (DSD, 2008)

Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links. - Dario Frazzetta; Giuseppe Dimartino; Maurizio Palesi; Shashi Kumar; Vincenzo Catania (DSD, 2008)

A Communication-Aware Topological Mapping Technique for NoCs. - Rafael Tornero; Juan M. Orduña; Maurizio Palesi; José Duato (Euro-Par, 2008)

Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms. - Maurizio Palesi; Giuseppe Longo; Salvatore Signorino; Rickard Holsmark; Shashi Kumar; Vincenzo Catania (NOCS, 2008)

Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions. - Rickard Holsmark; Maurizio Palesi; Shashi Kumar (J. Syst. Archit., 2008)

Reducing complexity of multiobjective design space exploration in VLIW-based embedded systems. - Vincenzo Catania; Maurizio Palesi; Davide Patti (ACM Trans. Archit. Code Optim., 2008)

Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip. - Giuseppe Ascia; Vincenzo Catania; Maurizio Palesi; Davide Patti (IEEE Trans. Computers, 2008)

An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded Architectures. - Vincenzo Catania; Alessandro G. Di Nuovo; Maurizio Palesi; Davide Patti; Gianmarco De Francisci Morales (DSD, 2009)

Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip. - Maurizio Palesi; Fabrizio Fazzino; Giuseppe Ascia; Vincenzo Catania (DSD, 2009)

A multi-objective strategy for concurrent mapping and routing in networks on chip. - Rafael Tornero; Valentino Sterrantino; Maurizio Palesi; Juan M. Orduña (IPDPS, 2009)

HiRA: A methodology for deadlock free routing in hierarchical networks on chip. - Rickard Holsmark; Shashi Kumar; Maurizio Palesi; Andres Mejia (NOCS, 2009)

Bandwidth-aware routing algorithms for networks-on-chip platforms. - Maurizio Palesi; Shashi Kumar; Vincenzo Catania (IET Comput. Digit. Tech., 2009)

Application Specific Routing Algorithms for Networks on Chip. - Maurizio Palesi; Rickard Holsmark; Shashi Kumar; Vincenzo Catania (IEEE Trans. Parallel Distributed Syst., 2009)

Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs. - Andres Mejia; Maurizio Palesi; José Flich; Shashi Kumar; Pedro López 001; Rickard Holsmark; José Duato (IEEE Trans. Very Large Scale Integr. Syst., 2009)

An Efficient Technique for In-order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip. - Maurizio Palesi; Rickard Holsmark; Xiaohang Wang 001; Shashi Kumar; Mei Yang 001; Yingtao Jiang; Vincenzo Catania (DSD, 2010)

A Multi-level Routing Scheme and Router Architecture to Support Hierarchical Routing in Large Network on Chip Platforms. - Rickard Holsmark; Shashi Kumar; Maurizio Palesi (Euro-Par Workshops, 2010)

Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks-on-Chip. - Maurizio Palesi; Shashi Kumar; Vincenzo Catania (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Application-Specific Routing Algorithms for Low Power Network on Chip Design. - Maurizio Palesi; Rickard Holsmark; Shashi Kumar; Vincenzo Catania (Low Power Networks-on-Chip, 2011)

Run-time deadlock detection in networks-on-chip using coupled transitive closure networks. - Ra'ed Al-Dujaily; Terrence S. T. Mak; Fei Xia 001; Alexandre Yakovlev; Maurizio Palesi (DATE, 2011)

Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip. - Xiaohang Wang 001; Maurizio Palesi; Mei Yang 001; Yingtao Jiang; Michael C. Huang 001; Peng Liu 016 (NPC, 2011)

Low latency and energy efficient multicasting schemes for 3D NoC-based SoCs. - Xiaohang Wang 001; Maurizio Palesi; Mei Yang 001; Yingtao Jiang; Michael C. Huang 001; Peng Liu 016 (VLSI-SoC, 2011)

Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems. - Giuseppe Ascia; Vincenzo Catania; Alessandro G. Di Nuovo; Maurizio Palesi; Davide Patti (Appl. Soft Comput., 2011)

Network-on-chip architectures and design methodologies. - Maurizio Palesi; Shashi Kumar; Radu Marculescu (Microprocess. Microsystems, 2011)

Data Encoding Schemes in Networks on Chip. - Maurizio Palesi; Giuseppe Ascia; Fabrizio Fazzino; Vincenzo Catania (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks. - Masoumeh Ebrahimi; Masoud Daneshtalab; Fahimeh Farahnakian; Juha Plosila; Pasi Liljeberg; Maurizio Palesi; Hannu Tenhunen (NOCS, 2012)

A Topology-Independent Mapping Technique for Application-Specific Networks-on-Chip. - Rafael Tornero; Maurizio Palesi; José Duato (Comput. Informatics, 2012)

Guest Editors' Introduction to the Special Issue on "Emerging Computing Architectures and Systems". - Fangyang Shen; Mei Yang 001; Maurizio Palesi (Comput. Electr. Eng., 2012)

Designing Robust Routing Algorithms and Mapping Cores in Networks-on-Chip: A Multi-objective Evolutionary-based Approach. - Maurizio Palesi; Rafael Tornero; Juan Manuel Orduña; Vincenzo Catania; Daniela Panno (J. Univers. Comput. Sci., 2012)

Supporting Undergraduate Computer Architecture Students Using a Visual MIPS64 CPU Simulator. - Davide Patti; Andrea Spadaccini; Maurizio Palesi; Fabrizio Fazzino; Vincenzo Catania (IEEE Trans. Educ., 2012)

Embedded Transitive Closure Network for Runtime Deadlock Detection in Networks-on-Chip. - Ra'ed Al-Dujaily; Terrence S. T. Mak; Fei Xia 001; Alex Yakovlev; Maurizio Palesi (IEEE Trans. Parallel Distributed Syst., 2012)

An Adaptive Output Selection Function Based on a Fuzzy Rule Base System for Network on Chip. - Giuseppe Ascia; Maurizio Palesi; Vincenzo Catania (DSD, 2013)

Runtime Online Links Voltage Scaling for Low Energy Networks on Chip. - Andrea Mineo; Maurizio Palesi; Giuseppe Ascia; Vincenzo Catania (DSD, 2013)

Message from the chairs. - Todor P. Stefanov; Maurizio Palesi; Jian-Jia Chen; Jörg Henkel (ESTIMedia, 2013)

Low Energy Mapping Techniques under Reliability and Bandwidth Constraints. - Andrea Mineo; Marina Masi; Maurizio Palesi; Giuseppe Ascia; Vincenzo Catania (HPCC/EUC, 2013)

On self-tuning networks-on-chip for dynamic network-flow dominance adaptation. - Xiaohang Wang 001; Terrence S. T. Mak; Mei Yang 001; Yingtao Jiang; Masoud Daneshtalab; Maurizio Palesi (NOCS, 2013)

NoC links energy reduction through link voltage scaling. - Andrea Mineo; Maurizio Palesi; Giuseppe Ascia; Vincenzo Catania (ICSAMOS, 2013)

Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip. - Xiaohang Wang 001; Peng Liu 016; Mei Yang 001; Maurizio Palesi; Yingtao Jiang; Michael C. Huang 001 (J. Comput. Sci. Technol., 2013)

Efficient multicast schemes for 3-D Networks-on-Chip. - Xiaohang Wang 001; Mei Yang 001; Yingtao Jiang; Maurizio Palesi; Peng Liu 016; Terrence S. T. Mak; Nader Bagherzadeh (J. Syst. Archit., 2013)

Guest Editors' Introduction to the Special Issue on "Novel On-Chip Parallel Architectures and Software Support". - Fangyang Shen; Mei Yang 001; Maurizio Palesi (Parallel Comput., 2013)

Introduction to the special section on on-chip and off-chip network architectures. - José Flich Cardo; Maurizio Palesi (ACM Trans. Embed. Comput. Syst., 2013)

Introduction to the special section on ESTIMedia'12. - Jian-Jia Chen; Maurizio Palesi (ACM Trans. Embed. Comput. Syst., 2013)

Merging Compilation and Microarchitectural Configuration Spaces for Performance/Power Optimization in VLIW-Based Systems. - Davide Patti; Maurizio Palesi; Vincenzo Catania (CSOC, 2014)

SHiFA: System-Level Hierarchy in Run-Time Fault-Aware Management of Many-Core Systems. - Mohammad Fattah; Maurizio Palesi; Pasi Liljeberg; Juha Plosila; Hannu Tenhunen (DAC, 2014)

An adaptive transmitting power technique for energy efficient mm-wave wireless NoCs. - Andrea Mineo; Maurizio Palesi; Giuseppe Ascia; Vincenzo Catania (DATE, 2014)

Adaptive power allocation for many-core systems inspired from multiagent auction model. - Xiaohang Wang 001; Baoxin Zhao; Terrence S. T. Mak; Mei Yang 001; Yingtao Jiang; Masoud Daneshtalab; Maurizio Palesi (DATE, 2014)

A Closed Loop Control based Power Manager for WiNoC Architectures. - Mohd Shahrizal Rusli; Andrea Mineo; Maurizio Palesi; Giuseppe Ascia; Vincenzo Catania; Muhammad N. Marsono (MES, 2014)

Introduction to the Special Issue on Network-on-Chip Architectures. - Masoud Daneshtalab; Maurizio Palesi; Terrence S. T. Mak (Comput. Electr. Eng., 2014)

Special issue on many-core embedded systems. - Masoud Daneshtalab; Maurizio Palesi; Juha Plosila; Ahmed Hemani (Microprocess. Microsystems, 2014)

Editorial: Special issue on design challenges for many-core processors. - Masoud Daneshtalab; Maurizio Palesi; Juha Plosila (ACM Trans. Embed. Comput. Syst., 2014)

Editorial: Special Section on ESTIMedia'13. - Maurizio Palesi; Todor P. Stefanov (ACM Trans. Embed. Comput. Syst., 2014)

On self-tuning networks-on-chip for dynamic network-flow dominance adaptation. - Xiaohang Wang 001; Mei Yang 001; Yingtao Jiang; Peng Liu 016; Masoud Daneshtalab; Maurizio Palesi; Terrence S. T. Mak (ACM Trans. Embed. Comput. Syst., 2014)

Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip. - Nima Jafarzadeh; Maurizio Palesi; Ahmad Khademzadeh; Ali Afzali-Kusha (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Noxim: An open, extensible and cycle-accurate network on chip simulator. - Vincenzo Catania; Andrea Mineo; Salvatore Monteleone; Maurizio Palesi; Davide Patti (ASAP, 2015)

A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures. - Andrea Mineo; Mohd Shahrizal Rusli; Maurizio Palesi; Giuseppe Ascia; Vincenzo Catania; Muhammad N. Marsono (DATE, 2015)

Message from the Chairs. - Hyunok Oh; Muhammad Shafique 001; Todor P. Stefanov; Maurizio Palesi (ESTIMedia, 2015)

Introduction to the special issue on NoC-based many-core architectures. - Masoud Daneshtalab; Maurizio Palesi; Terrence S. T. Mak (Comput. Electr. Eng., 2015)

Introduction to the special issue on "Emerging research in Internet of Things". - Fangyang Shen; Lingjia Liu 001; Maurizio Palesi (Comput. Electr. Eng., 2015)

Coupling Routing Algorithm and Data Encoding for Low Power Networks on Chip. - Maurizio Palesi; Davide Patti; Giuseppe Ascia; Daniela Panno; Vincenzo Catania (J. Comput. Sci., 2015)

Low Energy yet Reliable Data Communication Scheme for Network-on-Chip. - Nima Jafarzadeh; Maurizio Palesi; Saeedeh Eskandari; Shaahin Hessabi; Ali Afzali-Kusha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

An Offline Method for Designing Adaptive Routing Based on Pressure Model. - Minghua Tang; Xiaola Lin; Maurizio Palesi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Routing Pressure: A Channel-Related and Traffic-Aware Metric of Routing Algorithm. - Minghua Tang; Xiaola Lin; Maurizio Palesi (IEEE Trans. Parallel Distributed Syst., 2015)

Improving the energy efficiency of wireless Network on Chip architectures through online selective buffers and receivers shutdown. - Vincenzo Catania; Andrea Mineo; Salvatore Monteleone; Maurizio Palesi; Davide Patti (CCNC, 2016)

Energy efficient transceiver in wireless Network on Chip architectures. - Vincenzo Catania; Andrea Mineo; Salvatore Monteleone; Maurizio Palesi; Davide Patti (DATE, 2016)

Improved Flow Control for Minimal Fully Adaptive Routing in 2D Mesh NoC. - Alireza Monemi; Chia Yee Ooi; Muhammad Nadzir Marsono; Maurizio Palesi (NoCArc@MICRO, 2016)

Efficient Congestion-Aware Scheme for Wireless on-Chip Networks. - Amin Rezaei 001; Masoud Daneshtalab; Maurizio Palesi; Danella Zhao (PDP, 2016)

Special issue on energy efficient methods and systems in the emerging cloud era. - Maurizio Palesi; Mario Collotta; Masoud Daneshtalab; Pradip Bose (J. Comput. Syst. Sci., 2016)

Many-core System-on-Chip: architectures and applications. - Mohamed Bakhouya; Masoud Daneshtalab; Maurizio Palesi; Hassan Ghasemzadeh 001 (Microprocess. Microsystems, 2016)

Exploiting antenna directivity in wireless NoC architectures. - Andrea Mineo; Maurizio Palesi; Giuseppe Ascia; Vincenzo Catania (Microprocess. Microsystems, 2016)

Introduction to the special section on "Sustainable processor architectures and applications". - Fangyang Shen; Maurizio Palesi; Mei Yang 001 (Microprocess. Microsystems, 2016)

On-Chip Communication Energy Reduction Through Reliability Aware Adaptive Voltage Swing Scaling. - Andrea Mineo; Maurizio Palesi; Giuseppe Ascia; Partha Pratim Pande; Vincenzo Catania (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Cycle-Accurate Network on Chip Simulation with Noxim. - Vincenzo Catania; Andrea Mineo; Salvatore Monteleone; Maurizio Palesi; Davide Patti (ACM Trans. Model. Comput. Simul., 2016)

Local Congestion Avoidance in Network-on-Chip. - Minghua Tang; Xiaola Lin; Maurizio Palesi (IEEE Trans. Parallel Distributed Syst., 2016)

Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures. - Andrea Mineo; Maurizio Palesi; Giuseppe Ascia; Vincenzo Catania (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Energy aware Networks-on-Chip cortex inspired communication. - Erwan Moreac; Johann Laurent; Pierre Bomel; André Rossi; Emmanuel Boutillon; Maurizio Palesi (PATMOS, 2017)

ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform. - Alireza Monemi; Jia Wei Tang; Maurizio Palesi; Muhammad N. Marsono (Microprocess. Microsystems, 2017)

Ping-lock round robin arbiter. - Alireza Monemi; Chia Yee Ooi; Maurizio Palesi; Muhammad N. Marsono (Microelectron. J., 2017)

The Repetitive Turn Model for Adaptive Routing. - Minghua Tang; Xiaola Lin; Maurizio Palesi (IEEE Trans. Computers, 2017)

Approximate Wireless Networks-on-Chip. - Giuseppe Ascia; Vincenzo Catania; Salvatore Monteleone; Maurizio Palesi; Davide Patti; John Jose (DCIS, 2018)

Improving energy consumption of NoC based architectures through approximate communication. - Giuseppe Ascia; Vincenzo Catania; Salvatore Monteleone; Maurizio Palesi; Davide Patti; John Jose (MECO, 2018)

Critical Packet Prioritisation by Slack-Aware Re-Routing in On-Chip Networks. - Abhijit Das 002; Sarath Babu 003; John Jose; Sangeetha Jose; Maurizio Palesi (NOCS, 2018)

smARTworks: A Multi-sided Context-aware Platform for the Smart Museum. - Salvatore Michele Biondi; Vincenzo Catania; Salvatore Monteleone; Maurizio Palesi; Davide Patti (PECCS, 2018)

Packetization of Shared-Memory Traces for Message Passing Oriented NoC Simulation. - Vincenzo Catania; Salvatore Monteleone; Maurizio Palesi; Davide Patti (ISC, 2018)

Traffic Aware Deflection Rerouting Mechanism for Mesh Network on Chip. - Simi Zerine Sleeba; John Jose; Maurizio Palesi; Rekha K. James; Maniyelil Govindankutty Mini (VLSI-SoC, 2018)

An optimized hybrid algorithm in term of energy and performance for mapping real time workloads on 2d based on-chip networks. - Sarzamin Khan; Sheraz Anjum; Usman Ali Gulzari; Farruh Ishmanov; Maurizio Palesi; Muhammad Khalil Afzal (Appl. Intell., 2018)

Improving Energy Efficiency in Wireless Network-on-Chip Architectures. - Vincenzo Catania; Andrea Mineo; Salvatore Monteleone; Maurizio Palesi; Davide Patti (ACM J. Emerg. Technol. Comput. Syst., 2018)

The Suboptimal Routing Algorithm for 2D Mesh Network. - Minghua Tang; Jing Lin; Maurizio Palesi (IEEE Trans. Computers, 2018)

ACDC: An Accuracy- and Congestion-aware Dynamic Traffic Control Method for Networks-on-Chip. - Siyuan Xiao; Xiaohang Wang 001; Maurizio Palesi; Amit Kumar Singh 002; Terrence S. T. Mak (DATE, 2019)

Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices. - Giuseppe Ascia; Vincenzo Catania; Salvatore Monteleone; Maurizio Palesi; Davide Patti; John Jose (IoTSMS, 2019)

Study on logic-based routing for 3D NOCs. - Minghua Tang; Maurizio Palesi (NoCArc@MICRO, 2019)

Analyzing networks-on-chip based deep neural networks. - Giuseppe Ascia; Vincenzo Catania; Salvatore Monteleone; Maurizio Palesi; Davide Patti; John Jose (NOCS, 2019)

Performance Enhancement of Caches in TCMPs Using Near Vicinity Prefetcher. - Dipika Deb; John Jose; Maurizio Palesi (VLSID, 2019)

ECAP: energy-efficient caching for prefetch blocks in tiled chip multiprocessors. - Dipika Deb; John Jose; Maurizio Palesi (IET Comput. Digit. Tech., 2019)

Implementing On-Chip Wireless Communication in Multi-stage Interconnection NoCs. - Sirine Mnejja; Yassine Aydi; Mohamed Abid; Salvatore Monteleone; Maurizio Palesi; Davide Patti (AINA, 2020)

Cloud-Based Energy Efficient Scheme for Sigfox Monarch as Asset Tracking Service. - Andrea Mineo; Maurizio Palesi; Davide Patti; Vincenzo Catania (COINS, 2020)

DNNZip: Selective Layers Compression Technique in Deep Neural Network Accelerators. - Habiba Lahdhiri; Maurizio Palesi; Salvatore Monteleone; Davide Patti; Giuseppe Ascia; Jordane Lorandel; Emmanuelle Bourdel; Vincenzo Catania (DSD, 2020)

Efficient Compression Technique for NoC-based Deep Neural Network Accelerators. - Jordane Lorandel; Habiba Lahdhiri; Emmanuelle Bourdel; Salvatore Monteleone; Maurizio Palesi (DSD, 2020)

Improving Inference Latency and Energy of Network-on-Chip based Convolutional Neural Networks through Weights Compression. - Giuseppe Ascia; Vincenzo Catania; John Jose; Salvatore Monteleone; Maurizio Palesi; Davide Patti (IPDPS Workshops, 2020)

Exploiting On-Chip Routers to Store Dirty Cache Blocks in Tiled Chip Multi-processors. - Abhijit Das 002; Abhishek Kumar; John Jose; Maurizio Palesi (ISVLSI, 2020)

Improving Inference Latency and Energy of DNNs through Wireless Enabled Multi-Chip-Module-based Architectures and Model Parameters Compression. - Giuseppe Ascia; Vincenzo Catania; Andrea Mineo; Salvatore Monteleone; Maurizio Palesi; Davide Patti (NOCS, 2020)

Impact of Users' Beliefs in Text-Based Linguistic Interaction. - Vincenzo Catania; Salvatore Monteleone; Maurizio Palesi; Davide Patti (IEEE Access, 2020)

Introduction to the special section on intelligent computing systems and their applications. - Fangyang Shen; Mei Yang 001; Maurizio Palesi (Comput. Electr. Eng., 2020)

Guest Editorial: Communication-Aware Designs and Methodologies for Reliable and Adaptable On-Chip AI SubSystems and Accelerators. - Kun-Chih Chen; Masoumeh Ebrahimi; Maurizio Palesi; Tim Kogel (IEEE J. Emerg. Sel. Topics Circuits Syst., 2020)

An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators. - Seyed Morteza Nabavinejad; Mohammad Baharloo; Kun-Chih Chen; Maurizio Palesi; Tim Kogel; Masoumeh Ebrahimi (IEEE J. Emerg. Sel. Topics Circuits Syst., 2020)

Exploiting Data Resilience in Wireless Network-on-chip Architectures. - Giuseppe Ascia; Vincenzo Catania; Salvatore Monteleone; Maurizio Palesi; Davide Patti; John Jose; Valerio Mario Salerno (ACM J. Emerg. Technol. Comput. Syst., 2020)

Special issue on energy-efficient many-core embedded systems and architectures (SI: NoCArc18). - Maurizio Palesi; Kun-Chih Jimmy Chen; Midia Reshadi (J. Syst. Archit., 2020)

An Enhanced Dynamic Weighted Incremental Technique for QoS Support in NoC. - Alireza Monemi; Farshad Khunjush; Maurizio Palesi; Hamid Sarbazi-Azad (ACM Trans. Parallel Comput., 2020)

A Methodology for Simulating Multi-chiplet Systems Using Open-source Simulators. - Haocong Zhi; Xianuo Xu; Weijian Han; Zhilin Gao; Xiaohang Wang 001; Maurizio Palesi; Amit Kumar Singh 002; Letian Huang (NANOCOM, 2021)

LAMBDA: An Open Framework for Deep Neural Network Accelerators Simulation. - Enrico Russo 002; Maurizio Palesi; Salvatore Monteleone; Davide Patti; Giuseppe Ascia; Vincenzo Catania (PerCom Workshops, 2021)

Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach. - Nizar Dahir; Ammar Karkar; Maurizio Palesi; Terrence S. T. Mak; Alex Yakovlev (Integr., 2021)

Opportunistic Caching in NoC: Exploring Ways to Reduce Miss Penalty. - Abhijit Das 002; Abhishek Kumar; John Jose; Maurizio Palesi (IEEE Trans. Computers, 2021)

On Performance Optimization and Quality Control for Approximate-Communication-Enabled Networks-on-Chip. - Siyuan Xiao; Xiaohang Wang 001; Maurizio Palesi; Amit Kumar Singh 002; Liang Wang 020; Terrence S. T. Mak (IEEE Trans. Computers, 2021)

COPE: Reducing Cache Pollution and Network Contention by Inter-tile Coordinated Prefetching in NoC-based MPSoCs. - Dipika Deb; John Jose; Maurizio Palesi (ACM Trans. Design Autom. Electr. Syst., 2021)

MEDEA: A Multi-objective Evolutionary Approach to DNN Hardware Mapping. - Enrico Russo 002; Maurizio Palesi; Salvatore Monteleone; Davide Patti; Giuseppe Ascia; Vincenzo Catania (DATE, 2022)

Combined Application of Approximate Computing Techniques in DNN Hardware Accelerators. - Enrico Russo 002; Maurizio Palesi; Davide Patti; Habiba Lahdhiri; Salvatore Monteleone; Giuseppe Ascia; Vincenzo Catania (IPDPS Workshops, 2022)

Exploiting the Approximate Computing Paradigm with DNN Hardware Accelerators. - Enrico Russo 002; Maurizio Palesi; Salvatore Monteleone; Davide Patti; Habiba Lahdhiri; Giuseppe Ascia; Vincenzo Catania (MECO, 2022)

Analyzing the Impact of DNN Hardware Accelerators-Oriented Compression Techniques on General-Purpose Low-End Boards. - Giuliano Canzonieri; Salvatore Monteleone; Maurizio Palesi; Enrico Russo 002; Davide Patti (MobiWIS, 2022)

Revising NoC in Future Multicore-Based Consumer Electronics for Performance. - Abhijit Das 002; Abhishek Kumar; John Jose; Maurizio Palesi (IEEE Consumer Electron. Mag., 2022)

Multi-Objective Hardware-Mapping Co-Optimisation for Multi-Tenant DNN Accelerators. - Abhijit Das 002; Enrico Russo 002; Maurizio Palesi (CoRR, 2022)

Design Challenges of Intrachiplet and Interchiplet Interconnection. - Chixiao Chen; Jieming Yin; Yarui Peng; Maurizio Palesi; Wenxu Cao; Letian Huang; Amit Kumar Singh 002; Haocong Zhi; Xiaohang Wang 001 (IEEE Des. Test, 2022)

DNN Model Compression for IoT Domain-Specific Hardware Accelerators. - Enrico Russo 002; Maurizio Palesi; Salvatore Monteleone; Davide Patti; Andrea Mineo; Giuseppe Ascia; Vincenzo Catania (IEEE Internet Things J., 2022)

Memory-Aware DNN Algorithm-Hardware Mapping via Integer Linear Programming. - Enrico Russo 002; Maurizio Palesi; Giuseppe Ascia; Davide Patti; Salvatore Monteleone; Vincenzo Catania (CF, 2023)

Explainable AI-Based Clinical Decision Support System for Obesity Comorbidity Analysis. - Grazia Veronica Aiosa; Maurizio Palesi; Francesca Sapuppo; Maria Gabriella Xibilia (e-Science, 2023)

Wireless enabled Inter-Chiplet Communication in DNN Hardware Accelerators. - Maurizio Palesi; Enrico Russo 002; Abhijit Das 002; John Jose (IPDPS Workshops, 2023)

Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package. - Eduard Alarcón; Sergi Abadal; Fabio Sebastiano; Masoud Babaie; Edoardo Charbon; Peter Haring Bolívar; Maurizio Palesi; Elena Blokhina; Dirk Leipold; Robert Bogdan Staszewski; Artur García-Sáez; Carmen G. Almudéver (ISCAS, 2023)

m-BMC: Exploration of Magnetic Field Measurements for Indoor Positioning Using mini-Batch Magnetometer Calibration. - Hamaad Rafique; Davide Patti; Maurizio Palesi; Vincenzo Catania (MOST, 2023)

EXplainable AI for Decision Support to Obesity Comorbidities Diagnosis. - Grazia Veronica Aiosa; Maurizio Palesi; Francesca Sapuppo (IEEE Access, 2023)

A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures. - Fabrizio Ferrandi; Serena Curzel; Leandro Fiorin; Daniele Ielmini; Cristina Silvano; Francesco Conti 001; Alessio Burrello; Francesco Barchi; Luca Benini; Luciano Lavagno; Teodoro Urso; Enrico Calore; et al. (CoRR, 2023)

Multiobjective End-to-End Design Space Exploration of Parameterized DNN Accelerators. - Enrico Russo 002; Maurizio Palesi; Davide Patti; Salvatore Monteleone; Giuseppe Ascia; Vincenzo Catania (IEEE Internet Things J., 2023)

The position-based compression techniques for DNN model. - Minghua Tang; Enrico Russo 002; Maurizio Palesi (J. Supercomput., 2023)

A Novel Timechain-Level Approach to the Modeling of the Bitcoin Lightning Network. - Davide Patti; Salvatore Monteleone; Enrico Russo 002; Maurizio Palesi; Vincenzo Catania (Blockchain, 2024)

A Deep Reinforcement Learning based Online Scheduling Policy for Deep Neural Network Multi-Tenant Multi-Accelerator Systems. - Francesco Giulio Blanco; Enrico Russo 002; Maurizio Palesi; Davide Patti; Giuseppe Ascia; Vincenzo Catania (DAC, 2024)

Abstracting Bitcoin Lightning Network Complexity with Ultraviolet. - Davide Patti; Salvatore Monteleone; Enrico Russo 002; Maurizio Palesi; Vincenzo Catania (ICBC, 2024)

Characteristics-Based Least Common Multiple: A Novel Clustering Algorithm to Optimize Indoor Positioning. - Hamaad Rafique; Davide Patti; Maurizio Palesi; Gaetano Carmelo La Delfa (ICINCO (1), 2024)

Fusing Visuals with Magnetic Signals to Improve Indoor Localization Using Vision Transformer. - Hamaad Rafique; Davide Patti; Maurizio Palesi; Gaetano Carmelo La Delfa (IPIN, 2024)

Towards Fair and Firm Real-Time Scheduling in DNN Multi-Tenant Multi-Accelerator Systems via Reinforcement Learning. - Enrico Russo 002; Francesco Giulio Blanco; Maurizio Palesi; Giuseppe Ascia; Davide Patti; Vincenzo Catania (ISCAS, 2024)

Assessing the Role of Communication in Scalable Multi-Core Quantum Architectures. - Maurizio Palesi; Enrico Russo 002; Davide Patti; Giuseppe Ascia; Vincenzo Catania (MCSoC, 2024)

Data-Driven Simulation Based Fault Detection in Automotive RISC-V Applications. - Elio Vinciguerra; Enrico Russo 002; Maurizio Palesi; Giuseppe Ascia (MCSoC, 2024)

Lessons Learned on the Design of Cost-Effective and Highly Compatible Smart Gloves. - Marco Finocchiaro; Salvatore Monteleone; Enrico Russo 002; Maurizio Palesi; Davide Patti (MECO, 2024)

Improving LSTM-based Indoor Positioning via Simulation-Augmented Geomagnetic Field Dataset. - Elio Vinciguerra; Enrico Russo 002; Maurizio Palesi; Giuseppe Ascia; Hamaad Rafique (MOST, 2024)

Attention-Based Deep Reinforcement Learning for Qubit Allocation in Modular Quantum Architectures. - Enrico Russo 002; Maurizio Palesi; Davide Patti; Giuseppe Ascia; Vincenzo Catania (CoRR, 2024)

Correction to: The position-based compression techniques for DNN model. - Minghua Tang; Enrico Russo 002; Maurizio Palesi (J. Supercomput., 2024)

Multi-Objective Hardware-Mapping Co-Optimisation for Multi-DNN Workloads on Chiplet-Based Accelerators. - Abhijit Das 002; Enrico Russo 002; Maurizio Palesi (IEEE Trans. Computers, 2024)

Guest Editorial Chip and Package-Scale Communication-Aware Architectures for General-Purpose, Domain-Specific, and Quantum Computing Systems. - Abhijit Das 002; Maurizio Palesi; John Kim 001; Partha Pratim Pande (IEEE J. Emerg. Sel. Topics Circuits Syst., 2024)

Chip and Package-Scale Interconnects for General-Purpose, Domain-Specific, and Quantum Computing Systems - Overview, Challenges, and Opportunities. - Abhijit Das 002; Maurizio Palesi; John Kim 001; Partha Pratim Pande (IEEE J. Emerg. Sel. Topics Circuits Syst., 2024)

A Data-Driven Approach to Dataflow-Aware Online Scheduling for Graph Neural Network Inference. - Pol Puigdemont; Enrico Russo 002; Axel Wassington; Abhijit Das 002; Sergi Abadal; Maurizio Palesi (ASP-DAC, 2025)

Optimizing Qubit Assignment in Modular Quantum Systems via Attention-Based Deep Reinforcement Learning. - Enrico Russo 002; Maurizio Palesi; Davide Patti; Giuseppe Ascia; Vincenzo Catania (DATE, 2025)

Decentralized Framework for Teleportation in Quantum Core Interconnects. - P. S. Rajeswari Suance; Ruchika Gupta; Maurizio Palesi; John Jose (ISVLSI, 2025)

An Anomaly Detection Model for RISC-V in Automotive Applications: A Domain-Specific Accelerator Perspective. - Elio Vinciguerra; Enrico Russo 002; Maurizio Palesi; Giuseppe Ascia (PDP, 2025)

Indoor localization by projecting magnetic field signals onto images with vision transformer. - Hamaad Rafique; Davide Patti; Maurizio Palesi; Gaetano Carmelo La Delfa (Comput. Electr. Eng., 2025)

A Characteristics-Based Least Common Multiple Algorithm to Optimize Magnetic-Field-Based Indoor Localization. - Hamaad Rafique; Davide Patti; Maurizio Palesi; Gaetano Carmelo La Delfa (IEEE Internet Things J., 2025)

A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms. - Cristina Silvano; Daniele Ielmini; Fabrizio Ferrandi; Leandro Fiorin; Serena Curzel; Luca Benini; Francesco Conti 001; Angelo Garofalo; Cristian Zambelli; Enrico Calore; Sebastiano Fabio Schifano; Maurizio Palesi; et al. (ACM Comput. Surv., 2025)