Error Protected Data Bus Inversion Using Standard DRAM Components. - Maurizio Skerlj; Paolo Ienne (ISQED, 2008)

3D configuration caching for 2D FPGAs. - Alessandro Cevrero; Panagiotis Athanasopoulos; Hadi Parandeh-Afshar; Philip Brisk; Yusuf Leblebici; Paolo Ienne; Maurizio Skerlj (FPGA, 2009)

Using 3D integration technology to realize multi-context FPGAs. - Alessandro Cevrero; Panagiotis Athanasopoulos; Hadi Parandeh-Afshar; Maurizio Skerlj; Philip Brisk; Yusuf Leblebici; Paolo Ienne (FPL, 2009)