A non-deterministic scheduler for a software pipelining compiler. - Alessandro De Gloria; Paolo Faraboschi; Mauro Olivieri (MICRO, 1992)

An analysis of dynamic scheduling techniques for symbolic applications. - Alessandra Costa; Alessandro De Gloria; Paolo Faraboschi; Mauro Olivieri (MICRO, 1993)

An asynchronous approach to the RISC design of a micro-controller. - Alessandra Costa; Alessandro De Gloria; Paolo Faraboschi; Giovanni Nateri; Mauro Olivieri (Microprocess. Microprogramming, 1993)

A parallel architecture for the Color Doppler flow technique in ultrasound imaging. - Alessandra Costa; Alessandro De Gloria; Paolo Faraboschi; Mauro Olivieri (Microprocess. Microprogramming, 1993)

A delay insensitive approach to the VLSI design of a DRAM controller. - Alessandro De Gloria; Paolo Faraboschi; Mauro Olivieri (Microprocess. Microprogramming, 1993)

Design of a massively parallel SIMD architecture for the Boltzmann machine. - Alessandro De Gloria; Paolo Faraboschi; Mauro Olivieri (Microprocess. Microprogramming, 1993)

Delay insensitive micro-pipelined combinational logic. - Alessandro De Gloria; Paolo Faraboschi; Mauro Olivieri (Microprocess. Microprogramming, 1993)

Clustered Boltzmann Machines: Massively Parallel Architectures for Constrained Optimization Problems. - Alessandro De Gloria; Paolo Faraboschi; Mauro Olivieri (Parallel Comput., 1993)

Efficient implementation of the Boltzmann machine algorithm. - Alessandro De Gloria; Paolo Faraboschi; Mauro Olivieri (IEEE Trans. Neural Networks, 1993)

An evaluation system for distributed-time VHDL simulation. - Alessandra Costa; Alessandro De Gloria; Paolo Faraboschi; Mauro Olivieri (PADS, 1994)

Block placement with a Boltzmann Machine. - Alessandro De Gloria; Paolo Faraboschi; Mauro Olivieri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Efficient semicustom micropipeline design. - Alessandro De Gloria; Mauro Olivieri (IEEE Trans. Very Large Scale Integr. Syst., 1995)

Statistical Carry Lookahead Adders. - Alessandro De Gloria; Mauro Olivieri (IEEE Trans. Computers, 1996)

Hardware design of asynchronous fuzzy controllers. - Alessandra Costa; Alessandro De Gloria; Mauro Olivieri (IEEE Trans. Fuzzy Syst., 1996)

An asynchronous distributed architecture model for the Boltzmann machine control mechanism. - Alessandro De Gloria; Mauro Olivieri (IEEE Trans. Neural Networks, 1996)

Fuzzy logic microcontroller. - Alessandra Costa; Alessandro De Gloria; Fabrizio Giudici; Mauro Olivieri (IEEE Micro, 1997)

Delay-Insensitive Synthesis of the MCS 251 Microcontroller Core for Low Power Applications. - Alessandro De Gloria; Paolo Palma; Mauro Olivieri (EUROMICRO, 1999)

A Low-Power Microcontroller with on-Chip Self-Tuning Digital Clock-Generator for Variable-Load Applications. - Mauro Olivieri; Alessandro Trifiletti; Alessandro De Gloria (ICCD, 1999)

Semicustom Design of an IEEE 1394-Compliant Reusable IC Core. - Mauro Bertacchi; Alessandro De Gloria; Daniele Grosso; Mauro Olivieri (IEEE Des. Test Comput., 2000)

An application specific multi-port RAM cell circuit for register renaming units in high speed microprocessors. - Alessandro De Gloria; Mauro Olivieri (ISCAS (4), 2001)

A genetic approach to the design space exploration of superscalar microprocessor architectures. - Mauro Olivieri (ISCAS (5), 2001)

An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores. - Mauro Olivieri; Alessandro Trifiletti (ISCAS (4), 2001)

Design of synchronous and asynchronous variable-latency pipelined multipliers. - Mauro Olivieri (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Correction to "design of synchronous and asynchronous variable-latency pipelined multipliers". - Mauro Olivieri (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Theoretical system-level limits of power dissipation reduction under a performance constraint in VLSI microprocessor design. - Mauro Olivieri (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Power Efficiency of Application-Dependent Self-Configuring Pipeline Depth in DSP Microprocessors. - Mauro Olivieri; Marco Raspa (IPDPS, 2003)

A post-compiler approach to scratchpad mapping of code. - Federico Angiolini; Francesco Menichelli; Alberto Ferrero; Luca Benini; Mauro Olivieri (CASES, 2004)

A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design. - Francesco Menichelli; Mauro Olivieri; Luca Benini; Monica Donno; Labros Bisdounis (DATE, 2004)

Robust three-state PFD architecture with enhanced frequency acquisition capabilities. - Francesco Centurelli; Stefano Costi; Mauro Olivieri; Salvatore Pennisi; Alessandro Trifiletti (ISCAS (4), 2004)

Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV Techniques. - Mauro Olivieri; Mirko Scarana; Giuseppe Scotti; Alessandro Trifiletti (PATMOS, 2004)

A Class of Code Compression Schemes for Reducing Power Consumption in Embedded Microprocessor Systems. - Luca Benini; Francesco Menichelli; Mauro Olivieri (IEEE Trans. Computers, 2004)

Bus-switch coding for reducing power dissipation in off-chip buses. - Mauro Olivieri; Francesco Pappalardo 002; Giuseppe Visalli (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Software optimization of the JPEG2000 algorithm on a VLIW CPU core for system-on-chip implementation. - Francesco Menichelli; Mauro Olivieri; Simone Smorfa; Irene Zaccardini (Circuits, Signals, and Systems, 2005)

statistical analysis, for reducing the energy dissipation in a bus-switch encoder. - Mauro Olivieri; Francesco Pappalardo 002; Giuseppe Visalli (Circuits, Signals, and Systems, 2005)

Design issues for bus switch systems in deep sub-micro metric CMOS technologies. - Mauro Olivieri; Francesco Pappalardo 002; Giuseppe Visalli (Circuits, Signals, and Systems, 2005)

A novel CMOS logic style with data independent power consumption. - Manfred Josef Aigner; Stefan Mangard; Renato Menicocci; Mauro Olivieri; Giuseppe Scotti; Alessandro Trifiletti (ISCAS (2), 2005)

Encoding circuits for low power optical on-chip communications. - Mauro Olivieri; Francesco Pappalardo 002; Giuseppe Visalli (ISCAS (5), 2005)

Circuit-level power efficiency investigation of advanced DSP architectures based on a specialized power modeling technique. - Mauro Olivieri; Mirko Scarana; Simone Smorfa (ISCAS (5), 2005)

Design and Test of a Novel Programmable Clock Generator Semi-Custom Core for Energy-Efficient Systems-on-Chips. - Mauro Olivieri; Simone Smorfa; Alessandro Trifiletti (J. Low Power Electron., 2005)

A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control. - Mauro Olivieri; Giuseppe Scotti; Alessandro Trifiletti (IEEE Trans. Very Large Scale Integr. Syst., 2005)

MPARM: Exploring the Multi-Processor SoC Design Space with SystemC. - Luca Benini; Davide Bertozzi; Alessandro Bogliolo; Francesco Menichelli; Mauro Olivieri (J. VLSI Signal Process., 2005)

Side channel analysis resistant design flow. - Manfred Josef Aigner; Stefan Mangard; Francesco Menichelli; Renato Menicocci; Mauro Olivieri; Thomas Popp; Giuseppe Scotti; Alessandro Trifiletti (ISCAS, 2006)

A physical-level LCD driver model and simulator with application to pixel crosstalk suppression. - Simone Smorfa; Mauro Olivieri; Roberto Mancuso; Martin Lienhard (IEEE Trans. Consumer Electron., 2006)

A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations. - Francesco Centurelli; Luca Giancane; Mauro Olivieri; Giuseppe Scotti; Alessandro Trifiletti (PATMOS, 2007)

HW-SW optimisation of JPEG2000 wavelet transform for dedicated multimedia processor architectures. - Simone Smorfa; Mauro Olivieri (IET Comput. Digit. Tech., 2007)

Testing power-analysis attack susceptibility in register-transfer level designs. - Marco Bucci; Raimondo Luzzi; Francesco Menichelli; Renato Menicocci; Mauro Olivieri; Alessandro Trifiletti (IET Inf. Secur., 2007)

Analysis and Implementation of a Novel Leading Zero Anticipation Algorithm for Floating-Point Arithmetic Units. - Mauro Olivieri; Francesco Pappalardo 002; Simone Smorfa; Giuseppe Visalli (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A Reconfigurable, Low Power, Temperature Compensated IC for 8-segment Gamma Correction Curve in TFT, OLED and PDP Displays. - Mauro Olivieri; Roberto Mancuso; Friedbert Riedel (IEEE Trans. Consumer Electron., 2007)

A new dynamic differential logic style as a countermeasure to power analysis attacks. - Luca Giancane; Piero Marietti; Mauro Olivieri; Giuseppe Scotti; Alessandro Trifiletti (ICECS, 2008)

A novel high-quality YUV-based image coding technique for efficient image storage in portable electronic appliances. - Roberto Mancuso; Simone Smorfa; Mauro Olivieri (IEEE Trans. Consumer Electron., 2008)

High-Level Side-Channel Attack Modeling and Simulation for Security-Critical Systems on Chips. - Francesco Menichelli; Renato Menicocci; Mauro Olivieri; Alessandro Trifiletti (IEEE Trans. Dependable Secur. Comput., 2008)

LCD Design Techniques. - Simone Smorfa; Mauro Olivieri; Roberto Mancuso (Wiley Encyclopedia of Computer Science and Engineering, 2008)

Adaptive idleness distribution for non-uniform aging tolerance in MultiProcessor Systems-on-Chip. - Francesco Paterna; Luca Benini; Andrea Acquaviva; Francesco Papariello; Giuseppe Desoli; Mauro Olivieri (DATE, 2009)

Static Minimization of Total Energy Consumption in Memory Subsystem for Scratchpad-Based Systems-on-Chips. - Francesco Menichelli; Mauro Olivieri (IEEE Trans. Very Large Scale Integr. Syst., 2009)

TikTak: A Scalable Simulator of Wireless Sensor Networks Including Hardware/Software Interaction. - Francesco Menichelli; Mauro Olivieri (Wirel. Sens. Netw., 2010)

Performance evaluation of Jpeg2000 implementation on VLIW cores, SIMD cores and multi-cores. - Francesco Menichelli; Mauro Olivieri; Simone Smorfa (ISCAS, 2011)

Yield optimization for low power current controlled current conveyor. - Zia Abbas; Marat Yakupov; Mauro Olivieri; Andreas Ripp; Gunter Strube (SBCCI, 2012)

Delay-Tolerant, Low-Power Protocols for Large Security-Critical Wireless Sensor Networks. - Claudio Santo Malavenda; Francesco Menichelli; Mauro Olivieri (J. Comput. Networks Commun., 2012)

Wireless and Ad Hoc Sensor Networks: An Industrial Example Using Delay Tolerant, Low Power Protocols for Security-Critical Applications. - Claudio Santo Malavenda; Francesco Menichelli; Mauro Olivieri (ApplePies, 2013)

A flip-flop implementation for the DPA-resistant Delay-based Dual-rail Pre-charge Logic family. - Simone Bongiovanni; Mauro Olivieri; Giuseppe Scotti; Alessandro Trifiletti (MIXDES, 2013)

Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+). - Zia Abbas; Mauro Olivieri; Marat Yakupov; Andreas Ripp (Microelectron. J., 2013)

First integration of MOSFET band-to-band-tunneling current in BSIM4. - Fabrizio Ramundo; Paolo Nenzi; Mauro Olivieri (Microelectron. J., 2013)

A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures. - Mauro Olivieri; Antonio Mastrandrea (VLSI Design, 2013)

A Model-Based Methodology to Generate Code for Timer Units. - Marco Marazza; Francesco Menichelli; Mauro Olivieri; Orlando Ferrante; Alberto Ferrari (ApplePies, 2014)

A Platform-Based Emulator for Mass-Storage Flash Cards Evaluation in Embedded Systems. - Francesco Menichelli; Mauro Olivieri (ApplePies, 2014)

Combined Impact of NBTI Aging and Process Variations on Noise Margins of Flip-Flops. - Usman Khalid; Antonio Mastrandrea; Mauro Olivieri (DSD, 2014)

A Regulation-Based Security Evaluation Method for Data Link in Wireless Sensor Network. - Claudio Santo Malavenda; Francesco Menichelli; Mauro Olivieri (J. Comput. Networks Commun., 2014)

Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells. - Zia Abbas; Mauro Olivieri (Microelectron. J., 2014)

A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs. - Zia Abbas; Antonio Mastrandrea; Mauro Olivieri (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Logic Drivers: A Propagation Delay Modeling Paradigm for Statistical Simulation of Standard Cell Designs. - Mauro Olivieri; Antonio Mastrandrea (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Narrowband Delay Tolerant Protocols for WSN Applications: Characterization and Selection Guide. - Claudio Santo Malavenda; Francesco Menichelli; Mauro Olivieri (ApplePies, 2015)

Message from the general chairs. - Luca Benini; Renu Mehra; Mauro Olivieri (ISLPED, 2015)

Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops. - Usman Khalid; Antonio Mastrandrea; Mauro Olivieri (Microelectron. Reliab., 2015)

An Emulator for Approximate Memory Platforms Based on QEmu. - Francesco Menichelli; Giulia Stazi; Antonio Mastrandrea; Mauro Olivieri (ApplePies, 2016)

Optimal transistor sizing for maximum yield in variation-aware standard cell design. - Zia Abbas; Mauro Olivieri (Int. J. Circuit Theory Appl., 2016)

The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes. - Abdallah Cheikh; Gianmarco Cerutti; Antonio Mastrandrea; Francesco Menichelli; Mauro Olivieri (ApplePies, 2017)

Investigation on the Optimal Pipeline Organization in RISC-V Multi-threaded Soft Processor Cores. - Mauro Olivieri; Abdallah Cheikh; Gianmarco Cerutti; Antonio Mastrandrea; Francesco Menichelli (NGCAS, 2017)

Approximate Memory Support for Linux Early Allocators in ARM Architectures. - Giulia Stazi; Antonio Mastrandrea; Mauro Olivieri; Francesco Menichelli (ApplePies, 2018)

Synthesis Time Reconfigurable Floating Point Unit for Transprecision Computing. - Giulia Stazi; Federica Silvestri; Antonio Mastrandrea; Mauro Olivieri; Francesco Menichelli (ApplePies, 2018)

Characterizing noise pulse effects on the power consumption of idle digital cells. - Mauro Olivieri; Usman Khalid; Antonio Mastrandrea; Francesco Menichelli (ISCAS, 2018)

AppropinQuo: A Platform Emulator for Exploring the Approximate Memory Design Space. - Giulia Stazi; Antonio Mastrandrea; Mauro Olivieri; Francesco Menichelli (NGCAS, 2018)

Impact of Approximate Memory Data Allocation on a H.264 Software Video Encoder. - Giulia Stazi; Lorenzo Adani; Antonio Mastrandrea; Mauro Olivieri; Francesco Menichelli (ISC Workshops, 2018)

LEADER: Leakage Currents Estimation Technique for Aging Degradation Aware 16 nm CMOS Circuits. - Zia Abbas; Andleeb Zahra; Mauro Olivieri (VDAT, 2018)

A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer. - Luigi Blasi; Francesco Vigli; Abdallah Cheikh; Antonio Mastrandrea; Francesco Menichelli; Mauro Olivieri (ApplePies, 2019)

Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor. - Abdallah Cheikh; Stefano Sordillo; Antonio Mastrandrea; Francesco Menichelli; Mauro Olivieri (ApplePies, 2019)

Quality Aware Selective ECC for Approximate DRAM. - Giulia Stazi; Antonio Mastrandrea; Mauro Olivieri; Francesco Menichelli (ApplePies, 2019)

Quality Aware Approximate Memory in RISC-V Linux Kernel. - Giulia Stazi; Antonio Mastrandrea; Mauro Olivieri; Francesco Menichelli (PRIME, 2019)

The international race towards Exascale in Europe. - Fabrizio Gagliardi; Miquel Moretó; Mauro Olivieri; Mateo Valero (CCF Trans. High Perform. Comput., 2019)

Full System Emulation of Approximate Memory Platforms with AppropinQuo. - Giulia Stazi; Antonio Mastrandrea; Mauro Olivieri; Francesco Menichelli (J. Low Power Electron., 2019)

Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment. - Marcello Barbirotta; Antonio Mastrandrea; Francesco Menichelli; Francesco Vigli; Luigi Blasi; Abdallah Cheikh; Stefano Sordillo; Fabio Di Gennaro; Mauro Olivieri (DFT, 2020)

Klessydra-T: Designing Vector Coprocessors for Multi-Threaded Edge-Computing Cores. - Abdallah Cheikh; Stefano Sordillo; Antonio Mastrandrea; Francesco Menichelli; Giuseppe Scotti; Mauro Olivieri (CoRR, 2020)

SC-DDPL: A Novel Standard-Cell Based Approach for Counteracting Power Analysis Attacks in the Presence of Unbalanced Routing. - Davide Bellizia; Simone Bongiovanni; Mauro Olivieri; Giuseppe Scotti (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

The Italian research on HPC key technologies across EuroHPC. - Marco Aldinucci; Giovanni Agosta; Antonio Andreini; Claudio Agostino Ardagna; Andrea Bartolini; Alessandro Cilardo; Biagio Cosenza; Marco Danelutto; Roberto Esposito; William Fornaciari; Roberto Giorgi; Davide Lengani; et al. (CF, 2021)

A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design. - Marcello Barbirotta; Abdallah Cheikh; Antonio Mastrandrea; Francesco Menichelli; Francesco Vigli; Mauro Olivieri (DFT, 2021)

Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores. - Abdallah Cheikh; Stefano Sordillo; Antonio Mastrandrea; Francesco Menichelli; Giuseppe Scotti; Mauro Olivieri (IEEE Micro, 2021)

Contextual Bandits Algorithms for Reconfigurable Hardware Accelerators. - Marco Angioli; Marcello Barbirotta; Abdallah Cheikh; Antonio Mastrandrea; Francesco Menichelli; Saeid Jamili; Mauro Olivieri (ApplePies, 2022)

Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor. - Saeid Jamili; Abdallah Cheikh; Antonio Mastrandrea; Marcello Barbirotta; Francesco Menichelli; Marco Angioli; Mauro Olivieri (ApplePies, 2022)

BiSon-e: a lightweight and high-performance accelerator for narrow integer linear algebra computing on the edge. - Enrico Reggiani; Cristóbal Ramírez Lazo; Roger Figueras Bagué; Adrián Cristal; Mauro Olivieri; Osman Sabri Unsal (ASPLOS, 2022)

Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration. - Marcello Barbirotta; Abdallah Cheikh; Antonio Mastrandrea; Francesco Menichelli; Mauro Olivieri (PRIME, 2022)

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors. - Marcello Barbirotta; Abdallah Cheikh; Antonio Mastrandrea; Francesco Menichelli; Mauro Olivieri (IEEE Access, 2022)

Single Event Transient Reliability Analysis on a Fault-Tolerant RISC-V Microprocessor Design. - Marcello Barbirotta; Marco Angioli; Antonio Mastrandrea; Abdallah Cheikh; Saeid Jamili; Francesco Menichelli; Mauro Olivieri (ApplePies, 2023)

Heterogeneous Tightly-Coupled Dual Core Architecture Against Single Event Effects. - Marcello Barbirotta; Francesco Menichelli; Antonio Mastrandrea; Abdallah Cheikh; Marco Angioli; Saeid Jamili; Mauro Olivieri (ApplePies, 2023)

Alessandro De Gloria, a Pioneer in Electronic Engineering Applications. - Francesco Bellotti; Elisa Bricco; Agostino G. Bruzzone; Daniele D. Caviglia; Ermanno Di Zitti; Paolo Gastaldo; Daniele Grosso; Lauro Magnani; Mauro Olivieri; Marco Raggio; Maurizio Valle; Alessandro Verri; et al. (ApplePies, 2023)

A Universal Hardware Emulator for Verification IPs on FPGA: A Novel and Low-Cost Approach. - Saeid Jamili; Antonio Mastrandrea; Abdallah Cheikh; Marcello Barbirotta; Francesco Menichelli; Marco Angioli; Mauro Olivieri (ApplePies, 2023)

Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices. - Enrico Reggiani; Alessandro Pappalardo; Max Doblas; Miquel Moretó; Mauro Olivieri; Osman Sabri Unsal; Adrián Cristal (HPCA, 2023)

Automatic Hardware Accelerators Reconfiguration through LinearUCB Algorithms on a RISC-V Processor. - Marco Angioli; Marcello Barbirotta; Antonio Mastrandrea; Saeid Jamili; Mauro Olivieri (PRIME, 2023)

FAUST: Design and implementation of a pipelined RISC-V vector floating-point unit. - Mate Kovac; Leon Dragic; Branimir Malnar; Francesco Minervini; Oscar Palomar; Carlos Rojas; Mauro Olivieri; Josip Knezovic; Mario Kovac (Microprocess. Microsystems, 2023)

Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications. - Francesco Minervini; Oscar Palomar; Osman S. Unsal; Enrico Reggiani; Josue V. Quiroga; Joan Marimon; Carlos Rojas; Roger Figueras; Abraham Ruiz; Alberto González 004; Jonnatan Mendoza; Iván Vargas; et al. (ACM Trans. Archit. Code Optim., 2023)

Alternative Implementations of Error Correcting Codes in Register Files of a RISC-V Safety Critical Processor. - Marcello Barbirotta; Marco Angioli; Antonio Mastrandrea; Abdallah Cheikh; Francesco Menichelli; Mauro Olivieri (ApplePies, 2024)

Special Session: SE-UVM, an Integrated Simulation Environment for Single Event Induced Failures Characterization and its Application to the CV32E40P Processor. - Marcello Barbirotta; Marco Angioli; Antonio Mastrandrea; Francesco Menichelli; Abdallah Cheikh; Mauro Olivieri (DFT, 2024)

Dual-Modular-Redundancy Voting Circuits for Single-Event-Transient Mitigation. - Marcello Barbirotta; Marco Angioli; Antonio Mastrandrea; Francesco Menichelli; Abdallah Cheikh; Mauro Olivieri (DFT, 2024)

AeneasHDC: An Automatic Framework for Deploying Hyperdimensional Computing Models on FPGAs. - Marco Angioli; Saeid Jamili; Marcello Barbirotta; Abdallah Cheikh; Antonio Mastrandrea; Francesco Menichelli; Antonello Rosato; Mauro Olivieri (IJCNN, 2024)

Exploring Variable Latency Dividers in Vector Hardware Accelerators. - Marco Angioli; Marcello Barbirotta; Abdallah Cheikh; Antonio Mastrandrea; Mauro Olivieri (PRIME, 2024)

Dynamic Triple Modular Redundancy in Interleaved Hardware Threads: An Alternative Solution to Lockstep Multi-Cores for Fault-Tolerant Systems. - Marcello Barbirotta; Francesco Menichelli; Abdallah Cheikh; Antonio Mastrandrea; Marco Angioli; Mauro Olivieri (IEEE Access, 2024)

A RISC-V Fault-Tolerant Soft-Processor Based on Full/Partial Heterogeneous Dual-Core Protection. - Francesco Vigli; Marcello Barbirotta; Abdallah Cheikh; Francesco Menichelli; Antonio Mastrandrea; Mauro Olivieri (IEEE Access, 2024)

Enhancing Fault Tolerance in High-Performance Computing: A Real Hardware Case Study on a RISC-V Vector Processing Unit. - Marcello Barbirotta; Francesco Minervini; Carlos Rojas Morales; Adrián Cristal; Osman S. Unsal; Mauro Olivieri (IEEE Open J. Comput. Soc., 2024)

Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme. - Marco Angioli; Marcello Barbirotta; Abdallah Cheikh; Antonio Mastrandrea; Francesco Menichelli; Saeid Jamili; Mauro Olivieri (IEEE Trans. Computers, 2024)

HD-CB: The First Exploration of Hyperdimensional Computing for Contextual Bandits Problems. - Marco Angioli; Antonello Rosato; Marcello Barbirotta; Rocco Martino; Francesco Menichelli; Mauro Olivieri (CoRR, 2025)

Efficient Implementation of LinearUCB through Algorithmic Improvements and Vector Computing Acceleration for Embedded Learning Systems. - Marco Angioli; Marcello Barbirotta; Abdallah Cheikh; Antonio Mastrandrea; Francesco Menichelli; Mauro Olivieri (ACM Trans. Embed. Comput. Syst., 2025)