Accelerating Large-Scale Graph Analytics with FPGA and HMC. - Soroosh Khoram; Jialiang Zhang; Maxwell Strange; Jing Li 073 (FCCM, 2017)

Accelerating Graph Analytics by Co-Optimizing Storage and Access on an FPGA-HMC Platform. - Soroosh Khoram; Jialiang Zhang; Maxwell Strange; Jing Li 073 (FPGA, 2018)

Creating an Agile Hardware Design Flow. - Rick Bahr; Clark W. Barrett; Nikhil Bhagdikar; Alex Carsello; Ross Daly; Caleb Donovick; David Durst; Kayvon Fatahalian; Kathleen Feng; Pat Hanrahan; Teguh Hofstee; Mark Horowitz; et al. (DAC, 2020)

A-QED Verification of Hardware Accelerators. - Eshan Singh; Florian Lonsing; Saranyu Chattopadhyay; Maxwell Strange; Peng Wei 004; Xiaofan Zhang 001; Yuan Zhou; Deming Chen; Jason Cong; Priyanka Raina; Zhiru Zhang; Clark W. Barrett; et al. (DAC, 2020)

Automating System Configuration. - Nestan Tsiskaridze; Maxwell Strange; Makai Mann; Kavya Sreedhar; Qiaoyi Liu; Mark Horowitz; Clark W. Barrett (FMCAD, 2021)

Compiling Halide Programs to Push-Memory Accelerators. - Qiaoyi Liu; Dillon Huff; Jeff Setter; Maxwell Strange; Kathleen Feng; Kavya Sreedhar; Ziheng Wang; Keyi Zhang; Mark Horowitz; Priyanka Raina; Fredrik Kjolstad (CoRR, 2021)

Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration. - Kathleen Feng; Alex Carsello; Taeyoung Kong; Kalhan Koul; Qiaoyi Liu; Jackson Melchert; Gedeon Nyengele; Maxwell Strange; Keyi Zhang; Ankita Nayak; Jeff Setter; James Thomas 003; et al. (HCS, 2022)

Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra. - Alex Carsello; Kathleen Feng; Taeyoung Kong; Kalhan Koul; Qiaoyi Liu; Jackson Melchert; Gedeon Nyengele; Maxwell Strange; Keyi Zhang; Ankita Nayak; Jeff Setter; James Thomas 003; et al. (VLSI Technology and Circuits, 2022)

The Sparse Abstract Machine. - Olivia Hsu; Maxwell Strange; Ritvik Sharma; Jaeyeon Won; Kunle Olukotun; Joel S. Emer; Mark A. Horowitz; Fredrik Kjølstad (ASPLOS (3), 2023)

AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers. - Kalhan Koul; Jackson Melchert; Kavya Sreedhar; Leonard Truong; Gedeon Nyengele; Keyi Zhang; Qiaoyi Liu; Jeff Setter; Po-Han Chen; Yuchen Mei; Maxwell Strange; Ross Daly; et al. (ACM Trans. Embed. Comput. Syst., 2023)

Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators. - Qiaoyi Liu; Jeff Setter; Dillon Huff; Maxwell Strange; Kathleen Feng; Mark Horowitz; Priyanka Raina; Fredrik Kjolstad (ACM Trans. Archit. Code Optim., 2023)

Onyx: A Programmable Accelerator for Sparse Tensor Algebra. - Kalhan Koul; Maxwell Strange; Jackson Melchert; Alex Carsello; Yuchen Mei; Olivia Hsu; Taeyoung Kong; Po-Han Chen; Huifeng Ke; Keyi Zhang; Qiaoyi Liu; Gedeon Nyengele; et al. (HCS, 2024)

Onyx: A 12nm 756 GOPS/W Coarse-Grained Reconfigurable Array for Accelerating Dense and Sparse Applications. - Kalhan Koul; Maxwell Strange; Jackson Melchert; Alex Carsello; Yuchen Mei; Olivia Hsu; Taeyoung Kong; Po-Han Chen; Huifeng Ke; Keyi Zhang; Qiaoyi Liu; Gedeon Nyengele; et al. (VLSI Technology and Circuits, 2024)

Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra. - Kathleen Feng; Taeyoung Kong; Kalhan Koul; Jackson Melchert; Alex Carsello; Qiaoyi Liu; Gedeon Nyengele; Maxwell Strange; Keyi Zhang; Ankita Nayak; Jeff Setter; James Thomas 003; et al. (IEEE J. Solid State Circuits, 2024)

Designing Programmable Accelerators for Sparse Tensor Algebra. - Kalhan Koul; Zhouhua Xie; Maxwell Strange; Sai Gautham Ravipati; Bo-Wun Cheng; Olivia Hsu; Po-Han Chen; Mark Horowitz; Fredrik Kjolstad; Priyanka Raina (IEEE Micro, 2025)