Separation of concerns for hardware components of embedded systems in BIP. - Maya H. Safieddine; Rouwaida Kanj; Fadi A. Zaraket; Ali S. Elzein; Mohamad Jaber 001 (ISQED, 2015)

Automated FPGA implementations of BIP designs. - Maya H. Safieddine; Fadi A. Zaraket; Mohamad Jaber 001; Rouwaida Kanj; Mazen A. R. Saghir (SIES, 2016)

Verification at RTL Using Separation of Design Concerns. - Maya H. Safieddine; Fadi A. Zaraket; Rouwaida Kanj; Ali S. Elzein; Wolfgang Roesner (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)