Adder-Only Convolutional Neural Network with Binary Input Image. - Mayank Palaria; Sai Sanjeet; Bibhu Datta Sahoo 002; Masahiro Fujita (MWSCAS, 2019)

A Memristor-Based Analog Accelerator for Solving Quadratic Programming Problems. - Hsiang-Chun Cheng; Shiyu Su; Mayank Palaria; Qiaochu Zhang; Ce Yang; Sushmit Hossain; Ryan M. Bena; Buyun Chen; Zerui Liu; Juzheng Liu; Rezwan A. Rasul; Quan Nguyen 004; et al. (CICC, 2023)

Analog Kalman Filter with Integration and Digitization via a Shared Thyristor-Based VCO for Sensor Fusion in 65 nm CMOS. - Mayank Palaria; Shiyu Su; Hsiang-Chun Cheng; Rezwan A. Rasul; Qiaochu Zhang; Soumya Mahapatra; Chong-Fatt Law; Sushmit Hossain; Ryan M. Bena; Wei Wu; Quan Nguyen 004; Mike Shuo-Wei Chen (ESSCIRC, 2023)

A Stochastic Analog SAT Solver in 65nm CMOS Achieving 6.6μs Average Solution Time with 100% Solvability for Hard 3-SAT Problems. - Qiaochu Zhang; Shiyu Su; Zerui Liu; Hsiang-Chun Cheng; Zhengyi Qiu; Mayank Palaria; Jiacheng Ye; Deming Meng; Buyun Chen; Sushmit Hossain; Wei Wu; Mike Shuo-Wei Chen (VLSI Technology and Circuits, 2024)

26.1: A 24GHz Direct Digital Transmitter Using Multiphase Subharmonic Switching PA Achieving 3.2Gb/s Data Rate and -30.8dB EVM in 65nm CMOS. - Soumya Mahapatra; Mostafa M. Ayesh; Ce Yang; Mayank Palaria; Shiyu Su; Aoyang Zhang; Mike Shuo-Wei Chen (ISSCC, 2025)