Boolean factoring with multi-objective goals. - Mayler G. A. Martins; Leomar S. da Rosa Jr.; Anders B. Rasmussen; Renato P. Ribas; André Inácio Reis (ICCD, 2010)

Efficient method to compute minimum decision chains of Boolean functions. - Mayler G. A. Martins; Vinicius Callegaro; Renato P. Ribas; André Inácio Reis (ACM Great Lakes Symposium on VLSI, 2011)

Functional composition: A new paradigm for performing logic synthesis. - Mayler G. A. Martins; Renato P. Ribas; André Inácio Reis (ISQED, 2012)

KL-cut based digital circuit remapping. - Lucas Machado; Mayler G. A. Martins; Vinicius Callegaro; Renato P. Ribas; André Inácio Reis (NORCHIP, 2012)

Iterative remapping respecting timing constraints. - Lucas Machado; Mayler G. A. Martins; Vinicius Callegaro; Renato P. Ribas; André Inácio Reis (ISVLSI, 2013)

Read-polarity-once Boolean functions. - Vinicius Callegaro; Mayler G. A. Martins; Renato P. Ribas; André Inácio Reis (SBCCI, 2013)

Spin diode network synthesis using functional composition. - Mayler G. A. Martins; Felipe S. Marranghello; Joseph S. Friedman; Alan V. Sahakian; Renato P. Ribas; André Inácio Reis (SBCCI, 2013)

Synthesis of threshold logic gates to nanoelectronics. - Augusto Neutzling; Mayler G. A. Martins; Renato P. Ribas; André Inácio Reis (SBCCI, 2013)

Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible? - Matheus T. Moreira; Augusto Neutzling; Mayler G. A. Martins; André Inácio Reis; Renato P. Ribas; Ney Calazans (ASYNC, 2014)

A constructive approach for threshold logic circuit synthesis. - Augusto Neutzling; Mayler G. A. Martins; Renato P. Ribas; André Inácio Reis (ISCAS, 2014)

Methodology for achieving best trade-off of area and fault masking coverage in ATMR. - Iuri A. C. Gomes; Mayler G. A. Martins; Fernanda Lima Kastensmidt; André Inácio Reis; Renato P. Ribas; Sylvain P. Novales (LATW, 2014)

Enhanced Spin-Diode Synthesis Using Logic Sharing. - Mayler G. A. Martins; Felipe S. Marranghello; Joseph S. Friedman; Alan V. Sahakian; Renato P. Ribas; André Inácio Reis (DSD, 2015)

Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis. - Vinicius Callegaro; Felipe S. Marranghello; Mayler G. A. Martins; Renato P. Ribas; André Inácio Reis (ICCD, 2015)

Improved logic synthesis for memristive stateful logic using multi-memristor implication. - Felipe S. Marranghello; Vinicius Callegaro; Mayler G. A. Martins; André Inácio Reis; Renato P. Ribas (ISCAS, 2015)

Open Cell Library in 15nm FreePDK Technology. - Mayler G. A. Martins; Jody Maick Matos; Renato P. Ribas; André Inácio Reis; Guilherme Schlinker; Lucio Rech; Jens Michelsen (ISPD, 2015)

Using only redundant modules with approximate logic to reduce drastically area overhead in TMR. - Iuri A. C. Gomes; Mayler G. A. Martins; André Inácio Reis; Fernanda Lima Kastensmidt (LATS, 2015)

Factored Forms for Memristive Material Implication Stateful Logic. - Felipe S. Marranghello; Vinicius Callegaro; Mayler G. A. Martins; André Inácio Reis; Renato P. Ribas (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

Exploring the use of approximate TMR to mask transient faults in logic with low area overhead. - Iuri A. C. Gomes; Mayler G. A. Martins; André Inácio Reis; Fernanda Lima Kastensmidt (Microelectron. Reliab., 2015)

Virtual characterization for exhaustive DFM evaluation of logic cell libraries. - Samuel Pagliarini; Mayler G. A. Martins; Lawrence T. Pileggi (ISQED, 2017)

Improving approximate-TMR using multi-objective optimization genetic algorithm. - Iuri Albandes Cunha Gomes; Alejandro Serrano-Cases; Antonio J. Sanchez-Clemente; Mayler G. A. Martins; Antonio Martínez-Álvarez; Sergio Cuenca-Asensi; Fernanda Lima Kastensmidt (LATS, 2018)

Design of approximate-TMR using approximate library and heuristic approaches. - Iuri Albandes Cunha Gomes; Alejandro Serrano-Cases; Mayler G. A. Martins; Antonio Martínez-Álvarez; Sergio Cuenca-Asensi; Fernanda Lima Kastensmidt (Microelectron. Reliab., 2018)

A Simple and Effective Heuristic Method for Threshold Logic Identification. - Augusto Neutzling; Mayler G. A. Martins; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Application and Product-Volume-Specific Customization of BEOL Metal Pitch. - Samuel N. Pagliarini; Mehmet Meric Isgenc; Mayler G. A. Martins; Lawrence T. Pileggi (IEEE Trans. Very Large Scale Integr. Syst., 2018)

From Virtual Characterization to Test-Chips: DFM Analysis Through Pattern Enumeration. - Mayler G. A. Martins; Samuel N. Pagliarini; Mehmet Meric Isgenc; Lawrence T. Pileggi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Logic IP for Low-Cost IC Design in Advanced CMOS Nodes. - Mehmet Meric Isgenc; Mayler G. A. Martins; V. Mohammed Zackriya; Samuel N. Pagliarini; Lawrence T. Pileggi (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A Security-aware and LUT-based CAD Flow for the Physical Synthesis of eASICs. - Zain Ul Abideen 002; Tiago Diadami Perez; Mayler G. A. Martins; Samuel Pagliarini (CoRR, 2022)

A Security-Aware and LUT-Based CAD Flow for the Physical Synthesis of hASICs. - Zain Ul Abideen 002; Tiago Diadami Perez; Mayler G. A. Martins; Samuel Pagliarini (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)