Noise Margins of Threshold Logic Gates containing Resonant Tunneling Diodes. - Mayukh Bhattacharya; Pinaki Mazumder (Great Lakes Symposium on VLSI, 1998)

Circuit Design using Resonant Tunneling Diodes. - Pinaki Mazumder; Shriram Kulkarni; Mayukh Bhattacharya; Alejandro F. González (VLSI Design, 1998)

Digital circuit applications of resonant tunneling devices. - Pinaki Mazumder; Shriram Kulkarni; Mayukh Bhattacharya; Jian Ping Sun; George I. Haddad (Proc. IEEE, 1998)

A Physical Design Tool for Built-in Self-Repairable Static RAMs. - Kanad Chakraborty; Anurag Gupta; Mayukh Bhattacharya; Shriram Kulkarni; Pinaki Mazumder (DATE, 1999)

Simulation and emulation of digital integrated circuits containing resonant tunneling diodes. - Mayukh Bhattacharya (1999)

A prototyping technique for large-scale RTD-CMOS circuits. - Mayukh Bhattacharya; Shriram Kulkarni; Alejandro F. González; Pinaki Mazumder (ISCAS, 2000)

Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices. - Alejandro F. González; Mayukh Bhattacharya; Shriram Kulkarni; Pinaki Mazumder (ISMVL, 2000)

Convergence Issues in Resonant Tunneling Diode Circuit Simulation. - Mayukh Bhattacharya; Pinaki Mazumder (VLSI Design, 2000)

A 250-MHz, 32-bit quantum MOS correlator prototype. - Shriram Kulkarni; Mayukh Bhattacharya; Alejandro F. González; Pinaki Mazumder (ICECS, 2001)

Fd-Tlm Electromagnetic Field Simulation Of High-Speed Iii-V Heterojunction Bipolar Transistor Digital Logic Gates. - Mayukh Bhattacharya; Pinaki Mazumder; Ronald J. Lomax (VLSI Design, 2001)

Modeling of Nonuniform Interconnects by Using Differential Quadrature Method. - Qinwei Xu; Pinaki Mazumder; Mayukh Bhattacharya (VLSI Design, 2001)

CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices. - Alejandro F. González; Mayukh Bhattacharya; Shriram Kulkarni; Pinaki Mazumder (IEEE J. Solid State Circuits, 2001)

Augmentation of SPICE for simulation of circuits containingresonant tunneling diodes. - Mayukh Bhattacharya; Pinaki Mazumder (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

A physical design tool for built-in self-repairable RAMs. - Kanad Chakraborty; Shriram Kulkarni; Mayukh Bhattacharya; Pinaki Mazumder; Anurag Gupta (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Innovative practices on functional testing and fault simulation for FuSa. - Anandh Krishnan; John van Gelder; Mayukh Bhattacharya; Sreejit Chakravarty; Prashant Goteti (VTS, 2018)

A Structured Approach for Rapid Identification of Fault-Sensitive Nets in Analog Circuits. - Sayandeep Sanyal; Amit Patra; Pallab Dasgupta; Mayukh Bhattacharya (ATS, 2019)

Fault Classification and Coverage of Analog Circuits using DC Operating Point and Frequency Response Analysis. - Sayandeep Sanyal; Shan Pavan Pani Krishna Garapati; Amit Patra; Pallab Dasgupta; Mayukh Bhattacharya (ACM Great Lakes Symposium on VLSI, 2019)

A Methodology for Identification of Internal Nets for Improving Fault Coverage in Analog and Mixed Signal Circuits. - Sayandeep Sanyal; Mayukh Bhattacharya; Amit Patra; Pallab Dasgupta (J. Electron. Test., 2020)

Application of Sampling in Industrial Analog Defect Simulation. - Mayukh Bhattacharya; Beatrice Solignac; Michael Dürr (ITC, 2022)

Automatic Structural Test Generation for Analog Circuits using Neural Twins. - Jonti Talukdar; Arjun Chaudhuri; Mayukh Bhattacharya; Krishnendu Chakrabarty (ITC, 2022)

Accelerating Defect Simulation in Analog and Mixed-Signal Circuits by Parallel Defect Injection. - Sayandeep Sanyal; Mayukh Bhattacharya; Pallab Dasgupta; Amit Patra (VLSID, 2023)

DAWN: Efficient Trojan Detection in Analog Circuits Using Circuit Watermarking and Neural Twins. - Jayeeta Chaudhuri; Mayukh Bhattacharya; Krishnendu Chakrabarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Enhancing Analog IC Security Using Randomized Obfuscation Circuits. - Jayeeta Chaudhuri; Mayukh Bhattacharya; Krishnendu Chakrabarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)