A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems. - Kasho Yamamoto; Takashi Takemoto; Chihiro Yoshimura; Mayumi Mashimo; Masanao Yamaoka (A-SSCC, 2021)

4.6 A 144Kb Annealing System Composed of 9× 16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems. - Takashi Takemoto; Kasho Yamamoto; Chihiro Yoshimura; Masato Hayashi; Masafumi Tada; Hiroaki Saito; Mayumi Mashimo; Masanao Yamaoka (ISSCC, 2021)