Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures. - Meenakshi Kaul; Ranga Vemuri (DATE, 1998)

An Effective Design System for Dynamically Reconfigurable Architectures. - Sriram Govindarajan; Iyad Ouaiss; Meenakshi Kaul; Vinoo Srinivasan; Ranga Vemuri (FCCM, 1998)

An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures. - Iyad Ouaiss; Sriram Govindarajan; Vinoo Srinivasan; Meenakshi Kaul; Ranga Vemuri (IPPS/SPDP Workshops, 1998)

An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications. - Meenakshi Kaul; Ranga Vemuri; Sriram Govindarajan; Iyad Ouaiss (DAC, 1999)

Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs. - Meenakshi Kaul; Ranga Vemuri (DATE, 1999)

Integrated Block-Processing and Design-Space Exploration in Temporal Partitioning for RTR Architectures. - Meenakshi Kaul; Ranga Vemuri (IPPS/SPDP Workshops, 1999)

Design-Space Exploration for Block-Processing Based Temporal Partitioning of Run-Time Reconfigurable Systems. - Meenakshi Kaul; Ranga Vemuri (J. VLSI Signal Process., 2000)

An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications. - Ranga Vemuri; Srinivas Katkoori; Meenakshi Kaul; Jay Roy (ACM Trans. Design Autom. Electr. Syst., 2002)

Assessment of artificial intelligence-based digital learning systems in higher education amid the pandemic using analytic hierarchy. - Vikrant Vikram Singh; Nishant Kumar; Shailender Singh; Meenakshi Kaul; Aditya Kumar Gupta; P. K. Kapur 001 (Int. J. Syst. Assur. Eng. Manag., 2024)