ALIGN: Open-Source Analog Layout Automation from the Ground Up. - Kishor Kunal; Meghna Madhusudan; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Ramesh Harjani; Jiang Hu 001; Desmond A. Kirkpatrick; Sachin S. Sapatnekar (DAC, 2019)

Design Techniques for Zero Steady-State Output Ripple in Digital Low Dropout Regulators. - Saurabh Chaubey; Meghna Madhusudan; Ramesh Harjani (MWSCAS, 2019)

GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. - Kishor Kunal; Tonmoy Dhar; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Jiang Hu 001; Ramesh Harjani; Sachin S. Sapatnekar (DATE, 2020)

The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). - Tonmoy Dhar; Kishor Kunal; Yaguang Li; Yishuang Lin; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Steven M. Burns; Ramesh Harjani; Jiang Hu 001; Parijat Mukherjee; Soner Yaldiz; et al. (ICCAD, 2020)

A general approach for identifying hierarchical symmetry constraints for analog circuit layout. - Kishor Kunal; Jitesh Poojary; Tonmoy Dhar; Meghna Madhusudan; Ramesh Harjani; Sachin S. Sapatnekar (ICCAD, 2020)

A Customized Graph Neural Network Model for Guiding Analog IC Placement. - Yaguang Li; Yishuang Lin; Meghna Madhusudan; Arvind K. Sharma; Wenbin Xu; Sachin S. Sapatnekar; Ramesh Harjani; Jiang Hu 001 (ICCAD, 2020)

Learning from Experience: Applying ML to Analog Circuit Design. - Kishor Kunal; Tonmoy Dhar; Yaguang Li; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Ramesh Harjani; Jiang Hu 001; Parijat Mukherjee; Sachin S. Sapatnekar (ISPD, 2020)

Exploring a Machine Learning Approach to Performance Driven Analog IC Placement. - Yaguang Li; Yishuang Lin; Meghna Madhusudan; Arvind K. Sharma; Wenbin Xu; Sachin S. Sapatnekar; Ramesh Harjani; Jiang Hu 001 (ISVLSI, 2020)

Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models. - Tonmoy Dhar; Jitesh Poojary; Yaguang Li; Kishor Kunal; Meghna Madhusudan; Arvind K. Sharma; Susmita Dey Manasi; Jiang Hu 001; Ramesh Harjani; Sachin S. Sapatnekar (ASP-DAC, 2021)

Analog Layout Generation using Optimized Primitives. - Meghna Madhusudan; Arvind K. Sharma; Yaguang Li; Jiang Hu 001; Sachin S. Sapatnekar; Ramesh Hajiani (DATE, 2021)

Common-Centroid Layouts for Analog Circuits: Advantages and Limitations. - Arvind K. Sharma; Meghna Madhusudan; Steven M. Burns; Parijat Mukherjee; Soner Yaldiz; Ramesh Harjani; Sachin S. Sapatnekar (DATE, 2021)

From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. - Juzheng Liu; Shiyu Su; Meghna Madhusudan; Mohsen Hassanpourghadi; Samuel Saunders; Qiaochu Zhang; Rezwan A. Rasul; Yaguang Li; Jiang Hu 001; Arvind Kumar Sharma; Sachin S. Sapatnekar; Ramesh Harjani; et al. (ICCAD, 2021)

Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits. - Arvind K. Sharma; Meghna Madhusudan; Steven M. Burns; Soner Yaldiz; Parijat Mukherjee; Ramesh Harjani; Sachin S. Sapatnekar (ICCAD, 2021)

Machine Learning Techniques in Analog Layout Automation. - Tonmoy Dhar; Kishor Kunal; Yaguang Li; Yishuang Lin; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Steven M. Burns; Ramesh Harjani; Jiang Hu 001; Parijat Mukherjee; Soner Yaldiz; et al. (ISPD, 2021)

A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing. - Yaguang Li; Yishuang Lin; Meghna Madhusudan; Arvind K. Sharma; Sachin S. Sapatnekar; Ramesh Harjani; Jiang Hu 001 (MLCAD, 2021)

ALIGN: A System for Automating Analog Layout. - Tonmoy Dhar; Kishor Kunal; Yaguang Li; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Ramesh Harjani; Jiang Hu 001; Desmond A. Kirkpatrick; Parijat Mukherjee; et al. (IEEE Des. Test, 2021)

Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead. - Nibedita Karmokar; Meghna Madhusudan; Arvind K. Sharma; Ramesh Harjani; Mark Po-Hung Lin; Sachin S. Sapatnekar (ASP-DAC, 2022)

Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays. - Nibedita Karmokar; Arvind K. Sharma; Jitesh Poojary; Meghna Madhusudan; Ramesh Harjani; Sachin S. Sapatnekar (DATE, 2022)

Are Analytical Techniques Worthwhile for Analog IC Placement? - Yishuang Lin; Yaguang Li; Donghao Fang; Meghna Madhusudan; Sachin S. Sapatnekar; Ramesh Harjani; Jiang Hu 001 (DATE, 2022)

Analog/Mixed-Signal Layout Optimization using Optimal Well Taps. - Ramprasath S 001; Meghna Madhusudan; Arvind K. Sharma; Jitesh Poojary; Soner Yaldiz; Ramesh Harjani; Steven M. Burns; Sachin S. Sapatnekar (ISPD, 2022)

Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology. - Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Ramprasath S 001; Kishor Kunal; Sachin S. Sapatnekar; Ramesh Harjani (ESSDERC, 2023)

MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs. - Yishuang Lin; Yaguang Li; Meghna Madhusudan; Sachin S. Sapatnekar; Ramesh Harjani; Jiang Hu 001 (MLCAD, 2023)

Performance-driven Wire Sizing for Analog Integrated Circuits. - Yaguang Li; Yishuang Lin; Meghna Madhusudan; Arvind K. Sharma; Sachin S. Sapatnekar; Ramesh Harjani; Jiang Hu 001 (ACM Trans. Design Autom. Electr. Syst., 2023)

Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs. - Nibedita Karmokar; Arvind K. Sharma; Jitesh Poojary; Meghna Madhusudan; Ramesh Harjani; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

GNN-Based Hierarchical Annotation for Analog Circuits. - Kishor Kunal; Tonmoy Dhar; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Jiang Hu 001; Ramesh Harjani; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts. - Ramprasath Srinivasa Gopalakrishnan; Meghna Madhusudan; Arvind K. Sharma; Jitesh Poojary; Soner Yaldiz; Ramesh Harjani; Steven M. Burns; Sachin S. Sapatnekar (ACM Trans. Design Autom. Electr. Syst., 2023)

Reinforcing the Connection between Analog Design and EDA (Invited Paper). - Kishor Kunal; Meghna Madhusudan; Jitesh Poojary; S. Ramprasath 001; Arvind K. Sharma; Ramesh Harjani; Sachin S. Sapatnekar (ASPDAC, 2024)

Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients. - Arvind K. Sharma; Meghna Madhusudan; Steven M. Burns; Soner Yaldiz; Parijat Mukherjee; Ramesh Harjani; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)