A BIST Design of Structured Arrays with Fault-Tolerant Layout. - Mehdi Katoozi; Mani Soma (ITC, 1988)

Built-in test of CMOS state machines with realistic faults: a system perspective. - Mehdi Katoozi; Mani Soma (IEEE J. Solid State Circuits, 1990)

Low Overhead Built-In Testable Error Detection and Correction with Excellent Fault Coverage. - Mehdi Katoozi; Arnold Nordsiek (ITC, 1991)

Built-in testable error detection and correction. - Mehdi Katoozi; Arnold W. Nordsieck (IEEE J. Solid State Circuits, 1992)

Compact modeling and simulation of accelerated circuit aging. - Devyani Patra; Jiayang Zhang; Runsheng Wang; Mehdi Katoozi; Ethan H. Cannon; Ru Huang 001; Yu Cao 001 (CICC, 2018)

Accelerated BTI degradation under stochastic TDDB effect. - Devyani Patra; Ahmed Kamal Reza; Mehdi Katoozi; Ethan H. Cannon; Kaushik Roy 001; Yu Cao 001 (IRPS, 2018)

Adaptive accelerated aging for 28 nm HKMG technology. - Devyani Patra; Ahmed Kamal Reza; Mohammad Khaled Hassan; Mehdi Katoozi; Ethan H. Cannon; Kaushik Roy 001; Yu Cao 001 (Microelectron. Reliab., 2018)