Application-Specific Hardware-Driven Prefetching to Improve Data Cache Performance. - Mehdi Modarressi; Maziar Goudarzi; Shaahin Hessabi (Asia-Pacific Computer Systems Architecture Conference, 2005)

A Reconfigurable Cache Architecture for Object-Oriented Embedded Systems. - Mehdi Modarressi; Shaahin Hessabi; Maziar Goudarzi (CCECE, 2006)

A Data Prefetching Mechanism for Object-Oriented Embedded Systems Using Run-Time Profiling. - Mehdi Modarressi; Shaahin Hessabi; Maziar Goudarzi (DELTA, 2006)

A Table-Based Application-Specific Prefetch Engine for Object-Oriented Embedded Systems. - Shaahin Hessabi; Mehdi Modarressi; Maziar Goudarzi; Hani JavanHemmat (ICSAMOS, 2006)

Power-aware mapping for reconfigurable NoC architectures. - Mehdi Modarressi; Hamid Sarbazi-Azad (ICCD, 2007)

The 2D DBM: An attractive alternative to the simple 2D mesh topology for on-chip networks. - Reza Sabbaghi-Nadooshan; Mehdi Modarressi; Hamid Sarbazi-Azad (ICCD, 2008)

A novel high-performance and low-power mesh-based NoC. - Reza Sabbaghi-Nadooshan; Mehdi Modarressi; Hamid Sarbazi-Azad (IPDPS, 2008)

Virtual Point-to-Point Links in Packet-Switched NoCs. - Mehdi Modarressi; Hamid Sarbazi-Azad; Arash Tavakkol (ISVLSI, 2008)

A hybrid packet-circuit switched on-chip network based on SDM. - Mehdi Modarressi; Hamid Sarbazi-Azad; Mohammad Arjomand (DATE, 2009)

Performance and power efficient on-chip communication using adaptive virtual point-to-point connections. - Mehdi Modarressi; Hamid Sarbazi-Azad; Arash Tavakkol (NOCS, 2009)

An efficient dynamically reconfigurable on-chip network architecture. - Mehdi Modarressi; Hamid Sarbazi-Azad; Arash Tavakkol (DAC, 2010)

The 2D SEM: A novel high-performance and low-power mesh-based topology for networks-on-chip. - Reza Sabbaghi-Nadooshan; Mehdi Modarressi; Hamid Sarbazi-Azad (Int. J. Parallel Emergent Distributed Syst., 2010)

Virtual Point-to-Point Connections for NoCs. - Mehdi Modarressi; Arash Tavakkol; Hamid Sarbazi-Azad (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Energy-Optimized On-Chip Networks Using Reconfigurable Shortcut Paths. - Nasibeh Teimouri; Mehdi Modarressi; Arash Tavakkol; Hamid Sarbazi-Azad (ARCS, 2011)

Supporting non-contiguous processor allocation in mesh-based CMPs using virtual point-to-point links. - Marjan Asadinia; Mehdi Modarressi; Arash Tavakkol; Hamid Sarbazi-Azad (DATE, 2011)

A reconfigurable fault-tolerant routing algorithm to optimize the network-on-chip performance and latency in presence of intermittent and permanent faults. - Reyhaneh Jabbarvand Behrouz; Mehdi Modarressi; Hamid Sarbazi-Azad (ICCD, 2011)

Low-power arithmetic unit for DSP applications. - Mehdi Modarressi; Seyed Hossein Nikounia; Amir Hossein Jahangir (SoC, 2011)

A Distributed Task Migration Scheme for Mesh-Based Chip-Multiprocessors. - Hossein Yaghoubi; Mehdi Modarressi; Hamid Sarbazi-Azad (PDCAT, 2011)

Application-Aware Topology Reconfiguration for On-Chip Networks. - Mehdi Modarressi; Arash Tavakkol; Hamid Sarbazi-Azad (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Reconfigurable Cluster-Based Networks-on-Chip for Application-Specific MPSoCs. - Mehdi Modarressi; Hamid Sarbazi-Azad (ASAP, 2012)

A Game Theoretical Thermal - Aware Run - Time Task Synchronization Method for Multiprocessor Systems - on - Chip. - Yashar Asgarieh; Mohammad Hassan Khabbazian; Mehdi Modarressi; Hamid Sarbazi-Azad (DSD, 2012)

Supporting non-contiguous processor allocation in mesh-based chip multiprocessors using virtual point-to-point links. - Marjan Asadinia; Mehdi Modarressi; Hamid Sarbazi-Azad (IET Comput. Digit. Tech., 2012)

The 2D digraph-based NoCs: attractive alternatives to the 2D mesh NoCs. - Reza Sabbaghi-Nadooshan; Mehdi Modarressi; Hamid Sarbazi-Azad (J. Supercomput., 2012)

Power and Performance Efficient Partial Circuits in Packet-Switched Networks-on-Chip. - Nasibeh Teimouri; Mehdi Modarressi; Hamid Sarbazi-Azad (PDP, 2013)

Special issue on network-based many-core embedded systems. - Masoud Daneshtalab; Pasi Liljeberg; Mehdi Modarressi; Leandro Soares Indrusiak (J. Syst. Archit., 2013)

Using task migration to improve non-contiguous processor allocation in NoC-based CMPs. - Mehdi Modarressi; Marjan Asadinia; Hamid Sarbazi-Azad (J. Syst. Archit., 2013)

A reconfigurable network-on-chip architecture for heterogeneous CMPs in the dark-silicon era. - Mehdi Modarressi; Hamid Sarbazi-Azad (ASAP, 2014)

A hybrid packet/circuit-switched router to accelerate memory access in NoC-based chip multiprocessors. - Abbas Mazloumi; Mehdi Modarressi (DATE, 2015)

An energy-efficient virtual channel power-gating mechanism for on-chip networks. - Amirhossein Mirhosseini; Mohammad Sadrosadati; Ali Fakhrzadehgan; Mehdi Modarressi; Hamid Sarbazi-Azad (DATE, 2015)

Process variation-aware approximation for efficient timing management of digital circuits. - Mohsen Faryabi; Hamed Dorosti; Mehdi Modarressi; Sied Mehdi Fakhraie (EWDTS, 2015)

Hardware accelerator for biological protein sequence alignment on reconfigurable Networks-on-Chip. - Mehdi Modarressi; Faezeh Faghih; Maryam Modarressi (EWDTS, 2015)

CuPAN - High Throughput On-chip Interconnection for Neural Networks. - Ali Yasoubi; Reza Hojabr; Hengameh Takshi; Mehdi Modarressi; Masoud Daneshtalab (ICONIP (3), 2015)

Reconfigurable communication fabric for efficient implementation of neural networks. - Arash Firuzan; Mehdi Modarressi; Masoud Daneshtalab (ReCoSoC, 2015)

Improving the performance of packet-switched networks-on-chip by SDM-based adaptive shortcut paths. - Mehdi Modarressi; Nasibeh Teimouri; Hamid Sarbazi-Azad (Integr., 2015)

Leveraging dark silicon to optimize networks-on-chip topology. - Mehdi Modarressi; Hamid Sarbazi-Azad (J. Supercomput., 2015)

Integrated circuit-packet switching NoC with efficient circuit setup mechanism. - Farhad Pakdaman; Abbas Mazloumi; Mehdi Modarressi (J. Supercomput., 2015)

Fault-tolerant 3-D network-on-chip design using dynamic link sharing. - Seyyed Hossein Seyyedaghaei Rezaei; Mehdi Modarressi; Reza Yazdani Aminabadi; Masoud Daneshtalab (DATE, 2016)

Low-Power Online ECG Analysis Using Neural Networks. - Mehdi Modarressi; Ali Yasoubi; Maryam Modarressi (DSD, 2016)

A Three-Dimensional Networks-on-Chip Architecture with Dynamic Buffer Sharing. - Seyyed Hossein Seyyedaghaei Rezaei; Mehdi Modarressi; Masoud Daneshtalab; Shervin Roshanisefat (PDP, 2016)

SAMi: Self-aware migration approach for congestion reduction in NoC-based MCSoC. - Amin Rezaei 001; Masoud Daneshtalab; Dan Zhao 001; Mehdi Modarressi (SoCC, 2016)

Dynamic Resource Sharing for High-Performance 3-D Networks-on-Chip. - Seyyed Hossein Seyyedaghaei Rezaei; Abbas Mazloumi; Mehdi Modarressi; Pejman Lotfi-Kamran (IEEE Comput. Archit. Lett., 2016)

Power- and performance-efficient cluster-based network-on-chip with reconfigurable topology. - Pooyan Mehrvarzy; Mehdi Modarressi; Hamid Sarbazi-Azad (Microprocess. Microsystems, 2016)

An Efficient Hybrid-Switched Network-on-Chip for Chip Multiprocessors. - Pejman Lotfi-Kamran; Mehdi Modarressi; Hamid Sarbazi-Azad (IEEE Trans. Computers, 2016)

Parallel Forwarding for Efficient Bandwidth Utilization in Networks-on-Chip. - Elham Momenzadeh; Mehdi Modarressi; Abbas Mazloumi; Masoud Daneshtalab (ARCS, 2017)

A High-Performance Network-on-Chip Topology for Neuromorphic Architectures. - Nasrin Akbari; Mehdi Modarressi (CSE/EUC (2), 2017)

Near-Ideal Networks-on-Chip for Servers. - Pejman Lotfi-Kamran; Mehdi Modarressi; Hamid Sarbazi-Azad (HPCA, 2017)

Power-Efficient Accelerator Design for Neural Networks Using Computation Reuse. - Ali Yasoubi; Reza Hojabr; Mehdi Modarressi (IEEE Comput. Archit. Lett., 2017)

Thermal management in 3d networks-on-chip using dynamic link sharing. - Mahsa Keramati; Mehdi Modarressi; Seyed Hossein Seyedahaei Rezaei (Microprocess. Microsystems, 2017)

Customizing Clos Network-on-Chip for Neural Networks. - Reza Hojabr; Mehdi Modarressi; Masoud Daneshtalab; Ali Yasoubi; Ahmad Khonsari (IEEE Trans. Computers, 2017)

A Customized Processing-in-Memory Architecture for Biological Sequence Alignment. - Nasrin Akbari; Mehdi Modarressi; Masoud Daneshtalab; Mohammad Loni (ASAP, 2018)

Zone Based Control Methodology of Smart Indoor Lighting Systems Using Feedforward Neural Networks. - Atefesadat Seyedolhosseini; Nasser Masoumi; Mehdi Modarressi; Noushin Karimian (IST, 2018)

Design and Implementation of Efficient Smart Lighting Control System with Learning Capability for Dynamic Indoor Applications. - Atefesadat Seyedolhosseini; Nasser Masoumi; Mehdi Modarressi; Noushin Karimian (IST, 2018)

Reconfigurable Network-on-Chip for 3D Neural Network Accelerators. - Arash Firuzan; Mehdi Modarressi; Masoud Daneshtalab; Midia Reshadi (NOCS, 2018)

Chapter Six - Topology Specialization for Networks-on-Chip in the Dark Silicon Era. - Mehdi Modarressi; Hamid Sarbazi-Azad (Adv. Comput., 2018)

Fast Data Delivery for Many-Core Processors. - Mohammad Bakhshalipour; Pejman Lotfi-Kamran; Abbas Mazloumi; Farid Samandi; Mahmood Naderan-Tahan; Mehdi Modarressi; Hamid Sarbazi-Azad (IEEE Trans. Computers, 2018)

BARAN: Bimodal Adaptive Reconfigurable-Allocator Network-on-Chip. - Amirhossein Mirhosseini; Mohammad Sadrosadati; Fatemeh Aghamohammadi; Mehdi Modarressi; Hamid Sarbazi-Azad (ACM Trans. Parallel Comput., 2018)

NoM: Network-on-Memory for Inter-Bank Data Transfer in Highly-Banked Memories. - Seyyed Hossein Seyyedaghaei Rezaei; Mehdi Modarressi; Rachata Ausavarungnirun; Mohammad Sadrosadati; Onur Mutlu; Masoud Daneshtalab (IEEE Comput. Archit. Lett., 2020)

ΔNN: Power-Efficient Neural Network Acceleration Using Differential Weights. - Hoda Mahdiani; Alireza Khadem; Azam Ghanbari; Mehdi Modarressi; Farima Fattahi-Bayat; Masoud Daneshtalab (IEEE Micro, 2020)

Network-on-ReRAM for Scalable Processing-in-Memory Architecture Design. - Bita Dabiri; Mehdi Modarressi; Masoud Daneshtalab (DSD, 2021)

RoCo-NAS: Robust and Compact Neural Architecture Search. - Vahid Geraeinejad; Sima Sinaei; Mehdi Modarressi; Masoud Daneshtalab (IJCNN, 2021)

Multi-Precision Deep Neural Network Acceleration on FPGAs. - Negar Neda; Salim Ullah; Azam Ghanbari; Hoda Mahdiani; Mehdi Modarressi; Akash Kumar 001 (ASP-DAC, 2022)

Chapter Seven - Power-efficient network-on-chip design by partial topology reconfiguration. - Mehdi Modarressi; Seyyed Hossein Seyyedaghaei Rezaei (Adv. Comput., 2022)

Chapter One - Traffic-load-aware virtual channel power-gating in network-on-chips. - Mohammad Sadrosadati; Amirhossein Mirhosseini; Negar Akbarzadeh; Mehdi Modarressi; Hamid Sarbazi-Azad (Adv. Comput., 2022)

Reconfigurable Network-on-Chip based Convolutional Neural Network Accelerator. - Arash Firuzan; Mehdi Modarressi; Midia Reshadi; Ahmad Khademzadeh (J. Syst. Archit., 2022)

Energy-efficient acceleration of convolutional neural networks using computation reuse. - Azam Ghanbari; Mehdi Modarressi (J. Syst. Archit., 2022)

NeuroPIM: Felxible Neural Accelerator for Processing-in-Memory Architectures. - Ali Monavari Bidgoli; Sepideh Fattahi; Seyyed Hossein Seyyedaghaei Rezaei; Mehdi Modarressi; Masoud Daneshtalab (DDECS, 2023)

NCOD: Near-Optimum Video Compression for Object Detection. - Ardavan Elahi; Ali Falahati; Farhad Pakdaman; Mehdi Modarressi; Moncef Gabbouj (ISCAS, 2023)

Smart Memory: Deep Learning Acceleration in 3D-Stacked Memories. - Seyyed Hossein Seyyedaghaei Rezaei; Parham Zilouchian Moghaddam; Mehdi Modarressi (IEEE Comput. Archit. Lett., 2024)

NU-Class Net: A Novel Deep Learning-based Approach for Video Quality Enhancement. - Parham Zilouchian Moghaddam; Mehdi Modarressi; MohammadAmin Sadeghi (CoRR, 2024)

A novel deep learning-based approach for video quality enhancement. - Parham Zilouchian Moghaddam; Mehdi Modarressi; MohammadAmin Sadeghi (Eng. Appl. Artif. Intell., 2025)

A Customized Memory-aware Architecture for Biological Sequence Alignment. - Nasrin Akbari; Mehdi Modarressi; Alireza Khadem (CoRR, 2025)