Embedded Complex Floating Point Hardware Accelerator. - Amin Ghasemazar; Mehran Goli; Ali Afzali-Kusha (VLSID, 2014)

Application-specific power-aware mapping for reconfigurable NoC architectures. - Mehran Goli; Amin Ghasemazar; Zainalabedin Navabi (DTIS, 2015)

AIBA: An Automated Intra-cycle Behavioral Analysis for SystemC-based design exploration. - Mehran Goli; Jannis Stoppe; Rolf Drechsler (ICCD, 2016)

Automatic equivalence checking for SystemC-TLM 2.0 models against their formal specifications. - Mehran Goli; Jannis Stoppe; Rolf Drechsler (DATE, 2017)

Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed Automata. - Mehran Goli; Jannis Stoppe; Rolf Drechsler (ICCD, 2017)

Power Intent from Initial ESL Prototypes: Extracting Power Management Parameters*. - David Lemma; Mehran Goli; Daniel Große; Rolf Drechsler (NORCAS, 2018)

Resilience Evaluation for Approximating SystemC Designs Using Machine Learning Techniques. - Mehran Goli; Jannis Stoppe; Rolf Drechsler (RSP, 2018)

Scalable Simulation-Based Verification of SystemC-Based Virtual Prototypes. - Mehran Goli; Rolf Drechsler (DSD, 2019)

Automated Analysis of Virtual Prototypes at Electronic System Level. - Mehran Goli; Muhammad Hassan 002; Daniel Große; Rolf Drechsler (ACM Great Lakes Symposium on VLSI, 2019)

Security validation of VP-based SoCs using dynamic information flow tracking. - Mehran Goli; Muhammad Hassan 002; Daniel Große; Rolf Drechsler (it Inf. Technol., 2019)

Automatisierte Analyse virtueller Prototypen auf der ESL. - Mehran Goli (Ausgezeichnete Informatikdissertationen, 2019)

Towards Generation of a Programmable Power Management Unit at the Electronic System Level. - David Lemma; Mehran Goli; Daniel Große; Rolf Drechsler (DDECS, 2020)

ASCHyRO: Automatic Fault Localization of SystemC HLS Designs Using a Hybrid Accurate Rank Ordering Technique. - Mehran Goli; Alireza Mahzoon; Rolf Drechsler (ICCD, 2020)

Automated Design Understanding of SystemC-Based Virtual Prototypes: Data Extraction, Analysis and Visualization. - Mehran Goli; Rolf Drechsler (ISVLSI, 2020)

Automated Nonintrusive Analysis of Electronic System Level Designs. - Mehran Goli; Jannis Stoppe; Rolf Drechsler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

PREASC: Automatic Portion Resilience Evaluation for Approximating SystemC-based Designs Using Regression Analysis Techniques. - Mehran Goli; Rolf Drechsler (ACM Trans. Design Autom. Electr. Syst., 2020)

ATLaS: Automatic Detection of Timing-based Information Leakage Flows for SystemC HLS Designs. - Mehran Goli; Rolf Drechsler (ASP-DAC, 2021)

Early power estimation of CUDA-based CNNs on GPGPUs: work-in-progress. - Christopher A. Metz; Mehran Goli; Rolf Drechsler (CODES+ISSS, 2021)

Automated Debugging-Aware Visualization Technique for SystemC HLS Designs. - Mehran Goli; Alireza Mahzoon; Rolf Drechsler (DSD, 2021)

VIP-VP: Early Validation of SoCs Information Flow Policies using SystemC-based Virtual Prototypes. - Mehran Goli; Rolf Drechsler (FDL, 2021)

Early Validation of SoCs Security Architecture Against Timing Flows Using SystemC-based VPs. - Mehran Goli; Rolf Drechsler (ICCAD, 2021)

Pick the Right Edge Device: Towards Power and Performance Estimation of CUDA-based CNNs on GPGPUs. - Christopher A. Metz; Mehran Goli; Rolf Drechsler (CoRR, 2021)

Towards Polynomial Formal Verification of Complex Arithmetic Circuits. - Rolf Drechsler; Alireza Mahzoon; Mehran Goli (DDECS, 2022)

ML-based Power Estimation of Convolutional Neural Networks on GPGPUs. - Christopher A. Metz; Mehran Goli; Rolf Drechsler (DDECS, 2022)

Early Performance Estimation of Embedded Software on RISC-V Processor using Linear Regression. - Weiyan Zhang; Mehran Goli; Rolf Drechsler (DDECS, 2022)

Simulation-based Verification of SystemC-based VPs at the ESL. - Mehran Goli; Rolf Drechsler (MBMV, 2022)

Towards Neural Hardware Search: Power Estimation of CNNs for GPGPUs with Dynamic Frequency Scaling. - Christopher A. Metz; Mehran Goli; Rolf Drechsler (MLCAD, 2022)

ANN-based Performance Estimation of Embedded Software for RISC-V Processors. - Weiyan Zhang; Mehran Goli; Alireza Mahzoon; Rolf Drechsler (RSP, 2022)

Through the Looking Glass: Automated Design Understanding of SystemC-Based VPs at the ESL. - Mehran Goli; Rolf Drechsler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

EDDY: A Multi-Core BDD Package with Dynamic Memory Management and Reduced Fragmentation. - Rune Krauss; Mehran Goli; Rolf Drechsler (ASP-DAC, 2023)

Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - A RISC-V Case Study. - Sajjad Parvin; Mehran Goli; Frank Sill Torres; Rolf Drechsler (ASP-DAC, 2023)

FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing. - Sajjad Parvin; Mehran Goli; Frank Sill Torres; Rolf Drechsler (DATE, 2023)

Efficient Binary Decision Diagram Manipulation by Reducing the Number of Intermediate Nodes. - Rune Krauss; Mehran Goli; Rolf Drechsler (DDECS, 2023)

Efficient ML-Based Performance Estimation Approach Across Different Microarchitectures for RISC-V Processors. - Weiyan Zhang; Mehran Goli; Muhammad Hassan 002; Rolf Drechsler (DSD, 2023)

Fast and Accurate: Machine Learning Techniques for Performance Estimation of CNNs for GPGPUs. - Christopher A. Metz; Mehran Goli; Rolf Drechsler (IPDPS Workshops, 2023)

VAST: Validation of VP-based Heterogeneous Systems against Availability Security Properties using Static Information Flow Tracking. - Ece Nur Demirhan Coskun; Muhammad Hassan 002; Mehran Goli; Rolf Drechsler (ISQED, 2023)

Polynomial Formal Verification of a Processor: A RISC-V Case Study. - Lennart Weingarten; Alireza Mahzoon; Mehran Goli; Rolf Drechsler (ISQED, 2023)

LAT-UP: Exposing Layout-Level Analog Hardware Trojans Using Contactless Optical Probing. - Sajjad Parvin; Mehran Goli; Thilo Krachenfels; Shahin Tajik; Jean-Pierre Seifert; Frank Sill Torres; Rolf Drechsler (ISVLSI, 2023)

Early SoCs Information Flow Policies Validation Using SystemC-Based Virtual Prototypes at the ESL. - Mehran Goli; Rolf Drechsler (ACM Trans. Embed. Comput. Syst., 2024)

OPTI-Sim: Performing Optical Probing Simulation on Layout Design Files. - Sajjad Parvin; Mehran Goli; Frank Sill Torres; Rolf Drechsler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)