Fault Tolerant and Low Energy Write-Back Heterogeneous Set Associative Cache for DSM Technologies. - Mehrtash Manoochehri; Alireza Ejlali; Seyed Ghassem Miremadi (ARES, 2009)

Joint write policy and fault-tolerance mechanism selection for caches in DSM technologies: Energy-reliability trade-off. - Mehrtash Manoochehri; Alireza Ejlali; Seyed Ghassem Miremadi (ISQED, 2009)

CPPC: correctable parity protected cache. - Mehrtash Manoochehri; Murali Annavaram; Michel Dubois 001 (ISCA, 2011)

Soft error benchmarking of L2 caches with PARMA. - Jinho Suh; Mehrtash Manoochehri; Murali Annavaram; Michel Dubois 001 (SIGMETRICS, 2011)

Extremely Low Cost Error Protection with Correctable Parity Protected Cache. - Mehrtash Manoochehri; Murali Annavaram; Michel Dubois 001 (IEEE Trans. Computers, 2014)

Chip-independent Error Correction in main memories. - Mehrtash Manoochehri; Michel Dubois 001 (SAMOS, 2015)

Accurate Model for Application Failure Due to Transient Faults in Caches. - Mehrtash Manoochehri; Michel Dubois 001 (IEEE Trans. Computers, 2016)