Novel full-chip gridless routing considering double-via insertion. - Huang-Yu Chen; Mei-Fang Chiang; Yao-Wen Chang; Lumdo Chen; Brian Han (DAC, 2006)

Full-Chip Routing Considering Double-Via Insertion. - Huang-Yu Chen; Mei-Fang Chiang; Yao-Wen Chang; Lumdo Chen; Brian Han (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Register placement for high-performance circuits. - Mei-Fang Chiang; Takumi Okamoto; Takeshi Yoshimura (DATE, 2009)

Lagrangian relaxation based register placement for high-performance circuits. - Mei-Fang Chiang; Takumi Okamoto; Takeshi Yoshimura (ISQED, 2009)

Lagrangian Relaxation Based Inter-Layer Signal Via Assignment for 3-D ICs. - Song Chen 001; Liangwei Ge; Mei-Fang Chiang; Takeshi Yoshimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Redundant via Insertion: Removing Design Rule Conflicts and Balancing via Density. - Song Chen 001; Jianwei Shen 003; Wei Guo; Mei-Fang Chiang; Takeshi Yoshimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A compression-based area-efficient recovery architecture for nonvolatile processors. - Yiqun Wang; Yongpan Liu; Yumeng Liu; Daming Zhang; Shuangchen Li; Baiko Sai; Mei-Fang Chiang; Huazhong Yang (DATE, 2012)

A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops. - Yiqun Wang; Yongpan Liu; Shuangchen Li; Daming Zhang; Bo Zhao 003; Mei-Fang Chiang; Yanxin Yan; Baiko Sai; Huazhong Yang (ESSCIRC, 2012)

PaCC: A Parallel Compare and Compress Codec for Area Reduction in Nonvolatile Processors. - Yiqun Wang; Yongpan Liu; Shuangchen Li; Xiao Sheng; Daming Zhang; Mei-Fang Chiang; Baiko Sai; Xiaobo Sharon Hu; Huazhong Yang (IEEE Trans. Very Large Scale Integr. Syst., 2014)