Delay and Energy Efficient Data Transmission for On-Chip Buses. - Madhu Mutyam; Melvin Eze; Narayanan Vijaykrishnan; Yuan Xie 001 (ISVLSI, 2006)

Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect. - Melvin Eze; Ozcan Ozturk 001; Vijaykrishnan Narayanan (VLSI-SoC, 2013)