Sample-reset loop filter architecture for process independent and ripple-pole-less low jitter CMOS charge-pump PLLs. - Adrian Maxim; Baker Scott; Ed Schneider; Melvin Hagge; Steve Chacko; Dan Stiurca (ISCAS (4), 2001)

A low-jitter 125-1250-MHz process-independent and ripple-poleless 0.18-μm CMOS PLL based on a sample-reset loop filter. - Adrian Maxim; Baker Scott; Edmund M. Schneider; Melvin Hagge; Steve Chacko; Dan Stiurca (IEEE J. Solid State Circuits, 2001)