An Automatic Rectilinear Partitioning Procedure for Standard Cells. - Mely Chen Chi (DAC, 1987)

A Reliable Clock Tree Design Methodology for ASIC Designs. - Mely Chen Chi; Shih-Hsu Huang (ISQED, 2000)

A 0.75-mW analog processor IC for wireless biosignal monitor. - Chih-Jen Yen; Mely Chen Chi; Wen-Yaw Chung; Shing-Hao Lee (ISLPED, 2003)

Low-power driven standard-cell placement based on a multilevel force-directed algorithm. - Yu-Hsiung Huang; Mely Chen Chi (SoCC, 2004)

A Compact Low-Power Buffer Amplifier with Dynamic Bias Control Technique. - Chih-Jen Yen; Wen-Yaw Chung; Mely Chen Chi (VLSI Design, 2004)

Micro-power low-offset instrumentation amplifier IC design for biomedical system applications. - Chih-Jen Yen; Wen-Yaw Chung; Mely Chen Chi (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

An IR drop-driven placer for standard cells in a SOC design. - Jun Cheng Chi; Tsung Hui Huang; Mely Chen Chi (SoCC, 2005)

A Wide-Swing V_T-Referenced Circuit with Insensitivity to Device Mismatch. - Chih-Jen Yen; Wen-Yaw Chung; Mely Chen Chi (VLSI Design, 2005)

Gate Level Multiple Supply Voltage Assignment Algorithm for Power Optimization Under Timing Constraint. - Jun Cheng Chi; Hung Hsie Lee; Sung Han Tsai; Mely Chen Chi (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A multilevel multilayer partitioning algorithm for three dimensional integrated circuits. - Yu Cheng Hu; Yin Lin Chung; Mely Chen Chi (ISQED, 2010)

A layer prediction method for minimum cost three dimensional integrated circuits. - Tsu-Yun Hsueh; Hsiang-Hui Yang; Wei-Chieh Wu; Mely Chen Chi (ISQED, 2011)

NBTI-aware dual threshold voltage assignment for leakage power reduction. - Wen-Pin Tu; Shih-Wei Wu; Shih-Hsu Huang; Mely Chen Chi (ISCAS, 2012)

A 3D IC designs partitioning algorithm with power consideration. - Ho-lin Chang; Hsiang-Cheng Lai; Tsu-Yun Hsueh; Wei-Kai Cheng; Mely Chen Chi (ISQED, 2012)