ECG performance validation using operational transconductance amplifier with bias current. - Vallabhuni Vijay; C. V. Sai Kumar Reddy; Chandra Shaker Pittala; Rajeev Ratna Vallabhuni; M. Saritha; M. Lavanya; S. China Venkateswarlu; Menda Sreevani (Int. J. Syst. Assur. Eng. Manag., 2021)

A VLSI design of clock gated technique based ADC lock-in amplifier. - M. Saritha; M. Lavanya; G. Ajitha; Mulinti Narendra Reddy; P. Annapurna; Menda Sreevani; S. Swathi; S. Sushma; Vallabhuni Vijay (Int. J. Syst. Assur. Eng. Manag., 2022)

State-of-art design: data selectors using quantum-dot cellular automata. - Menda Sreevani; Vallabhuni Vijay; Kancharapu Chaitanya; Chelle Radhika; Nandi Manjula; D. Radha Krishna Koushik; B. Sai Venumadhav; T. Sai Jaideep; Chandra Shaker Pittala; Sadulla Shaik (Int. J. Syst. Assur. Eng. Manag., 2024)

Advanced arithmetic circuits realization using next generation logic gates. - Menda Sreevani; Sivaji Satrasupalli; Rajeev Ratna Vallabhuni; S. China Venkateswarlu (Int. J. Syst. Assur. Eng. Manag., 2025)