Placement with Alignment and Performance Constraints Using the B*-Tree Representation. - Meng-Chen Wu; Yao-Wen Chang (ICCD, 2004)

Performance Constraints Aware Voltage Islands Generation in SoC Floorplan Design. - Ming-Ching Lu; Meng-Chen Wu; Hung-Ming Chen; Iris Hui-Ru Jiang (SoCC, 2006)

Multiple-Fault Diagnosis Using Faulty-Region Identification. - Meng-Jai Tasi; Mango Chia-Tso Chao; Jing-Yang Jou; Meng-Chen Wu (VTS, 2009)

Performance-constrained voltage assignment in multiple supply voltage SoC floorplanning. - Meng-Chen Wu; Ming-Ching Lu; Hung-Ming Chen; Jing-Yang Jou (ACM Trans. Design Autom. Electr. Syst., 2009)

Mixed non-rectangular block packing for non-Manhattan layout architectures. - Meng-Chen Wu; Hung-Ming Chen; Jing-Yang Jou (ISQED, 2011)

Design-for-debug layout adjustment for FIB probing and circuit editing. - Kuo-An Chen; Tsung-Wei Chang; Meng-Chen Wu; Mango Chia-Tso Chao; Jing-Yang Jou; Sonair Chen (ITC, 2011)

On Near-Optimal Codebook and Receiver Designs for MIMO-SCMA Schemes. - Yen-Ming Chen; Yu-Chen Hsu; Meng-Chen Wu; Rupender Singh; Yuan-Chu Chang (IEEE Trans. Wirel. Commun., 2022)

qFD: Coherent and Depolarizing Fault Diagnosis for Quantum Processors. - Yen-Wei Li; Cheng-Yun Hsieh; Meng-Chen Wu; James Chien-Mo Li (ITC, 2024)

SEEval: Advancing LLM Text Evaluation Efficiency and Accuracy through Self-Explanation Prompting. - Meng-Chen Wu; Md Mosharaf Hossain; Tess Wood; Shayan Ali Akbar; Si-Chi Chin; Erwin Cornejo (NAACL (Findings), 2025)