A new pipelined adaptive DFE architecture with improved convergence rate. - Meng-Da Yang; An-Yeu Wu (ISCAS (4), 2002)

Fast convergent pipelined adaptive DFE architecture using post-cursor processing filter technique. - Meng-Da Yang; An-Yeu Wu; Jyh-Ting Lai (IEEE Trans. Circuits Syst. II Express Briefs, 2004)

High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme. - Meng-Da Yang; An-Yeu Wu; Jyh-Ting Lai (IEEE Trans. Very Large Scale Integr. Syst., 2004)