A 24μW 12b 1MS/s 68.3dB SNDR SAR ADC with two-step decision DAC switching. - Yung-Hui Chung; Meng-Hsuan Wu; Hung-Sung Li (CICC, 2013)

A 1V 9pA analog front end with compressed sensing for electrocardiogram monitoring. - Liang-Ting Kuo; Chun-Chih Hou; Meng-Hsuan Wu; Yun-Shiang Shu (A-SSCC, 2015)

A 12-bit 8.47-fJ/Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS. - Yung-Hui Chung; Meng-Hsuan Wu; Hung-Sung Li (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A 24- μW 12-bit 1-MS/s SAR ADC With Two-Step Decision DAC Switching in 110-nm CMOS. - Yung-Hui Chung; Chia-Wei Yen; Meng-Hsuan Wu (IEEE Trans. Very Large Scale Integr. Syst., 2016)

High-Precision UWB Indoor Positioning System for Customer Pathway Tracking. - Yuan-Hao Ho; Guan-Hao Hou; Meng-Hsuan Wu; Fu-Hsing Chen; Pi-Shan Sung; Chieh-Hsu Chen; Chih-Lung Lin (GCCE, 2019)

DTW-based Motion Matching System in Consumer Shopping Interest Analysis. - Meng-Hsuan Wu; You-Hong Liu; Chieh-Hsu Chen; Peng-Ting Chen; Chih-Lung Lin (GCCE, 2021)

Actions Speak Louder than Listening: Evaluating Music Style Transfer based on Editing Experience. - Wei Tsung Lu; Meng-Hsuan Wu; Yuh-Ming Chiu; Li Su 004 (ACM Multimedia, 2021)

Evaluation of Novel Cognitive Assessment System for Testing Visual Memory of the Elderly. - Chih-Lung Lin; Ting-Ching Chu; Meng-Hsuan Wu; Ming-Yang Deng; Wen-Ching Chiu; Chien-Hsu Chen; Pi-Shan Sung; Wen-Lung Tsao; Tsung-Chih Lin (IEEE Access, 2021)

Residual Echo Suppression using Spatial Feature for Stereo Acoustic Echo Cancellation. - Hsuan-Cheng Chou; Yih-Liang Shen; Meng-Hsuan Wu; Bo-Wun Shih; Tai-Shih Chi (APSIPA ASC, 2023)

A Dual-Channel Three-Stage Model for DoA and Speech Enhancement. - Meng-Hsuan Wu; Yih-Liang Shen; Hsuan-Cheng Chou; Bo-Wun Shih; Tai-Shih Chi (APSIPA ASC, 2023)

Multispectral Imaging for Preliminary Burn Depth Evaluation in Mice with Tissue Section Analysis. - Yu-Hsien Lu; Meng-Hsuan Wu; Yu-Zheng Chen; Po-Liang Ou; Kuo-Shu Hung; Yi-Syuan Shin; Yuan-Yu Hsueh; Peng-Ting Chen; Chih-Lung Lin (IEEE SENSORS, 2024)

36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating. - Mu-Shan Lin; Chien-Chun Tsai; Shenggao Li; Wei-Chih Chen; Wen-Hung Huang; Yu-Chi Chen; Yu-Jie Huang; Alan J. Drake; Chin-Hua Wen; Paul Ranucci; Hsin-Hung Kuo; Aidong Yin; et al. (ISSCC, 2025)