Low power design of phase-change memory based on a comprehensive model. - Meng-Hsueh Chiang; Yi-Bo Liao; Jun-Tin Lin; Wei-Chou Hsu; Chu Yu; Pei-Chia Chiang; Y.-Y. Hsu; W.-H. Liu; Shyh-Shyuan Sheu; Keng-Li Su; Ming-Jer Kao; Ming-Jinn Tsai (IET Comput. Digit. Tech., 2010)

Design issues and insights of multi-fin bulk silicon FinFETs. - Hsun Li; Meng-Hsueh Chiang (ISQED, 2012)

Assessment of structure variation in silicon nanowire FETs and impact on SRAM. - Yi-Bo Liao; Meng-Hsueh Chiang; Keunwoo Kim; Wei-Chou Hsu (Microelectron. J., 2012)

6-T SRAM performance assessment with stacked silicon nanowire MOSFETs. - Ya-Chi Huang; Meng-Hsueh Chiang; Wei-Chou Hsu; Shiou-Ying Cheng (ISQED, 2015)

Performance evaluation of stacked gate-all-around MOSFETs at 7 and 10 nm technology nodes. - Meng-Yen Wu; Meng-Hsueh Chiang (ISQED, 2016)

Threshold-voltage variability analysis and modeling for junctionless double-gate transistors. - Chun-Yu Chen; Jyi-Tsong Lin; Meng-Hsueh Chiang (Microelectron. Reliab., 2017)

An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires. - Ya-Chi Huang; Meng-Hsueh Chiang; Shui-Jinn Wang; Sumeet Kumar Gupta (ICICDT, 2018)

Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM. - Jheng-Yi Chen; Ming-Yu Chang; Shi-Hao Chen; Jia-Wei Lee; Meng-Hsueh Chiang (ISQED, 2018)

Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications. - Ya-Chi Huang; Meng-Hsueh Chiang; Shui-Jinn Wang (ISQED, 2019)

Compact Device Models for FinFET and Beyond. - Darsen D. Lu; Mohan V. Dunga; Ali M. Niknejad; Chenming Hu; Fu-Xiang Liang; Wei-Chen Hung; Jia-Wei Lee; Chun-Hsiang Hsu; Meng-Hsueh Chiang (CoRR, 2020)

Back-Bias Modulated UTBB SOI for System-on-Chip I/O Cells. - Ming-Yu Chang; Po-Yu Chao; Meng-Hsueh Chiang (ISQED, 2021)

Performance Comparison of SRAM Designs Implemented with Silicon-On-Insulator Nanosheet Transistors and Bulk FinFETs. - Po-Chih Chen; Yi-Ting Wu; Meng-Hsueh Chiang (ESSDERC, 2023)

MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization. - W.-C. Lin; H.-P. Huang; Kuo-Hsing Kao; Meng-Hsueh Chiang; Darsen D. Lu; Wei-Chou Hsu; Yeong-Her Wang; William Cheng-Yu Ma; Hann-Huei Tsai; Y.-J. Lee; H.-L. Chiang; J.-F. Wang; et al. (ESSDERC, 2023)

How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology. - H.-L. Chiang; Richard A. Hadi; J.-F. Wang; Hung-Chi Han; J.-J. Wu; H.-H. Hsieh; J.-J. Horng; W.-S. Chou; B.-S. Lien; C.-H. Chang; Y.-C. Chen; Yeong-Her Wang; et al. (VLSI Technology and Circuits, 2023)

Fabrication of Hybrid Fin/Planar LDMOS with Modulation Gate. - Zih-Fei Chen; Ya-Chi Huang; Yu-Shen Lai; Yi-Ting Wu; Cheng-Ming Huang; Meng-Hsueh Chiang (DRC, 2024)