Optimization of clock mesh based on wire sizing variation. - Meng Liu 018; Zhiwei Zhang; Wenqin Sun; Donglin Wang (ISOCC, 2017)

Obstacle-aware symmetrical clock tree construction. - Meng Liu 018; Zhiwei Zhang; Wenqin Sun; Donglin Wang (MWSCAS, 2017)

A novel obstacle-aware multiple fan-out symmetrical clock tree synthesis. - Meng Liu 018; Zhiwei Zhang; Wenqin Sun; Donglin Wang (IEICE Electron. Express, 2017)

HcveAcc: A High-Performance and Energy-Efficient Accelerator for Tracking Task in VSLAM System. - Renwei Li; Junning Wu; Meng Liu 018; Zuding Chen; Shengang Zhou; Shanggong Feng (DATE, 2020)

The RISC-V instruction set architecture optimization and fixed-point math library co-design: work-in-progress. - Meng Liu 018 (CODES+ISSS, 2021)

An Approximate Symmetry Clock Tree Design with Routing Topology Prediction. - Meng Liu 018; Zhiye Zhang; Jiabao Wen; Yunpeng Jia (MWSCAS, 2021)

A co-design method of customized ISA design space exploration and fixed-point library construction for RISC-V dedicated processor. - Meng Liu 018 (IEICE Electron. Express, 2022)

Vector-Based Dedicated Processor Architecture for Efficient Tracking in VSLAM Systems. - Dejian Li; Xi Feng; Chongfei Shen; Qi Chen; Lixin Yang; Sihai Qiu; Xin Jin; Meng Liu 018 (IEEE Embed. Syst. Lett., 2023)

SSRESF: Sensitivity-aware Single-particle Radiation Effects Simulation Framework in SoC Platforms based on SVM Algorithm. - Meng Liu 018; Shuai Li; Fei Xiao; Ruijie Wang; Chunxue Liu; Liang Wang 024 (DAC, 2024)

Clock mesh synthesis through dynamic programming with physical parameters consideration. - Dejian Li; Jie Gan; Chongfei Shen; Qi Chen; Lixin Yang; Sihai Qiu; Xin Jin; Tiantian Wu; Zhijie Chen; Meng Liu 018 (Integr., 2025)

PttAcc: Pipeline-Based Taylor Expansion Fitting Arctangent Angle Hardware Accelerator Design for Descriptor Duty in ORB-SLAM System. - Meng Liu 018; Fei Xiao; Ruijie Wang; Peiyuan Wan; Zhijie Chen; Dejian Li; Chongfei Shen (IEEE Embed. Syst. Lett., 2025)